-
公开(公告)号：US10353832B2
公开(公告)日：2019-07-16
申请号：US15995711
申请日：2018-06-01
Inventor： Matthias Fromme , Jochen Sauer , Matthias Schmitz
Abstract: A number of software routines comprising at least two software routines are created for an interface unit of a computer system having a first and a second interface processor for forwarding input data from a peripheral to a processor of the computer system on which software is programmed. A first subset of the software routines is assigned to a first category provided for task-synchronous data transfer, and a second subset of the software routines are assigned to a second category provided for continuous data transfer. The first interface processor is programmed with the first subset and the second interface processor with the second subset of software routines. During execution of the software, the first subset is cyclically executed by the first interface processor at a first cycle rate, and the second subset is cyclically executed by the second interface processor at a second cycle rate.
-
公开(公告)号：US10747649B2
公开(公告)日：2020-08-18
申请号：US15996850
申请日：2018-06-04
Inventor： Matthias Fromme , Jochen Sauer , Matthias Schmitz
Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.
-
公开(公告)号：US10055363B2
公开(公告)日：2018-08-21
申请号：US15151746
申请日：2016-05-11
Inventor： Jochen Sauer , Robert Leinfellner , Matthias Klemm , Thorsten Brehm , Robert Polnau , Matthias Schmitz
IPC: G06F13/00 , G06F13/10 , G06F13/12 , G06F13/20 , G06F13/40 , G06F9/445 , G06F15/78 , G11C8/18 , G06F13/38 , G06F9/4401
CPC classification number: G06F13/102 , G06F9/4411 , G06F9/44505 , G06F13/126 , G06F13/20 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F15/7885 , G11C8/18
Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
-
公开(公告)号：US10180917B2
公开(公告)日：2019-01-15
申请号：US15151767
申请日：2016-05-11
Inventor： Jochen Sauer , Robert Leinfellner , Matthias Klemm , Thorsten Brehm , Robert Polnau , Matthias Schmitz
IPC: G06F13/10 , G06F13/40 , G11C8/18 , G06F15/78 , G06F9/445 , G06F13/20 , G06F13/12 , G06F13/38 , G06F9/4401
Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
-
-
-
Search Results
4
records
(took 0.015 seconds)
