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公开(公告)号：US11283344B2
公开(公告)日：2022-03-22
申请号：US17158626
申请日：2021-01-26
申请人： pSemi Corporation
摘要： Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.
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公开(公告)号：US20240259014A1
公开(公告)日：2024-08-01
申请号：US18435509
申请日：2024-02-07
申请人： pSemi Corporation
IPC分类号： H03K17/082 , H03K5/08
CPC分类号： H03K17/0822 , H03K5/086
摘要： Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.
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公开(公告)号：US20210226526A1
公开(公告)日：2021-07-22
申请号：US17158626
申请日：2021-01-26
申请人： pSemi Corporation
摘要： Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.
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公开(公告)号：US11942860B2
公开(公告)日：2024-03-26
申请号：US17331594
申请日：2021-05-26
申请人： pSemi Corporation
IPC分类号： H02M3/07 , H02M1/08 , H03K17/687
CPC分类号： H02M3/07 , H02M1/08 , H03K17/687
摘要： Circuits and methods to mitigate or eliminate potentially damaging events (e.g., damaging current spikes from in-rush current, charge transfer current, short circuits, etc.) in DC-DC power converters. Embodiments enable dynamic switching of conversion ratios in reconfigurable power converters while under load without turning off the power converter circuitry or suspending switching of the charge pump power switches. Embodiments selectively increase the ON resistance, RON, for at least some power FETs in a power converter by actively controlling the driver voltage to the gates of the power FETs. During normal operation, the power FET driver voltage may be set to overdrive the FET gate to lower RON to a desired level that allows high current flow. For other scenarios, the power FET driver voltage may be reduced so as to increase RON while ON and thus impede current flow to provide protection against potentially damaging events.
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公开(公告)号：US20230120452A1
公开(公告)日：2023-04-20
申请号：US17968440
申请日：2022-10-18
申请人： pSemi Corporation
摘要： Circuits and methods for protecting the switches of charge pump-based power converters from damage if a VOUT short circuit event occurs and/or if VIN falls rapidly with respect to VX or VOUT. A general embodiment includes a VX Detection Block coupled to the core block of a power converter. The VX Detection Block is coupled to VX and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in VX during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VIN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of VIN to the power converter. The VIN Detection Block is coupled to VIN, and to VX or VOUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
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公开(公告)号：US10594202B1
公开(公告)日：2020-03-17
申请号：US16277779
申请日：2019-02-15
申请人： pSemi Corporation
摘要： Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.
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公开(公告)号：US11936371B1
公开(公告)日：2024-03-19
申请号：US17959904
申请日：2022-10-04
申请人： pSemi Corporation
IPC分类号： H03K17/08 , H03K5/08 , H03K17/082
CPC分类号： H03K17/0822 , H03K5/086
摘要： Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.
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公开(公告)号：US11482931B2
公开(公告)日：2022-10-25
申请号：US16783800
申请日：2020-02-06
申请人： pSemi Corporation
摘要： Circuits and methods for protecting the switches of charge pump-based power converters from damage if a VOUT short circuit event occurs and/or if VIN falls rapidly with respect to VX or VOUT. A general embodiment includes a VX Detection Block coupled to the core block of a power converter. The VX Detection Block is coupled to VX and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in VX during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VIN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of VIN to the power converter. The VIN Detection Block is coupled to VIN, and to VX or VOUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
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公开(公告)号：US20210249955A1
公开(公告)日：2021-08-12
申请号：US16783800
申请日：2020-02-06
申请人： pSemi Corporation
摘要： Circuits and methods for protecting the switches of charge pump-based power converters from damage if a VOUT short circuit event occurs and/or if VIN falls rapidly with respect to VX or VOUT. A general embodiment includes a VX Detection Block coupled to the core block of a power converter. The VX Detection Block is coupled to VX and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in VX during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VIN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of VIN to the power converter. The VIN Detection Block is coupled to VIN, and to VX or VOUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
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公开(公告)号：US20240120837A1
公开(公告)日：2024-04-11
申请号：US17960712
申请日：2022-10-05
申请人： pSemi Corporation
CPC分类号： H02M3/157 , H02M1/0022 , H02M1/0038
摘要： Circuits and methods for selectable conversion ratio power converters that include low-dropout (LDO) power supplies adapted to select voltage inputs based on the selected conversion ratio while achieving high efficiency. The LDO power supplies limit current through power FETs of power converters, thereby mitigating or eliminating potentially damaging events. In some embodiments, first and second full gate-drive LDOs have “wired-OR” outputs which may power a target circuit such as a pre-driver (and optionally, a level-shifter) coupled to the gate of a power FET. In some embodiments, first and second reduced gate-drive LDOs have “wired-OR” outputs that may power a final driver coupled to the gate of a power FET. Some embodiments have dual full gate-drive LDOs that power a target circuit such as a pre-driver (and optionally, a level-shifter), while dual reduced gate-drive LDOs that power a final driver coupled to the gate of the power FET.
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