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17 条记录 (耗时 0.015 秒)

    Loopback testing of integrated circuits
    3.
    发明授权
    Loopback testing of integrated circuits 有权

    公开(公告)号：US12123908B1

    公开(公告)日：2024-10-22

    申请号：US18367333

    申请日：2023-09-12

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Shai Cohen ,  Evelyn Landman

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3177

    CPC分类号： G01R31/2896 ,  G01R31/31727 ,  G01R31/3177

    摘要： Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.

    Integrated circuit margin measurement and failure prediction device
    4.
    发明授权
    Integrated circuit margin measurement and failure prediction device 有权

    公开(公告)号：US11385282B2

    公开(公告)日：2022-07-12

    申请号：US16764056

    申请日：2018-11-15

    申请人： PROTEANTECS LTD.

    发明人： Evelyn Landman ,  Shai Cohen ,  Yahel David ,  Eyal Fayneh ,  Inbar Weintrob

    IPC分类号： G01R31/28 ,  G01R31/30

    摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

    Thermal sensor for integrated circuit
    5.
    发明授权
    Thermal sensor for integrated circuit 有权

    公开(公告)号：US11619551B1

    公开(公告)日：2023-04-04

    申请号：US17750637

    申请日：2022-05-23

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Shaked Rahamim ,  Evelyn Landman

    IPC分类号： G01K7/00 ,  G01K7/01 ,  G01K15/00

    摘要： A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.

    Integrated circuit I/O integrity and degradation monitoring
    6.
    发明授权
    Integrated circuit I/O integrity and degradation monitoring 有权

    公开(公告)号：US10740262B2

    公开(公告)日：2020-08-11

    申请号：US16729680

    申请日：2019-12-30

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Evelyn Landman ,  Shai Cohen ,  Guy Redler ,  Inbar Weintrob

    IPC分类号： G06F3/00 ,  G06F13/16 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    摘要： An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

    Die-to-die and chip-to-chip connectivity monitoring
    7.
    发明授权
    Die-to-die and chip-to-chip connectivity monitoring 有权

    公开(公告)号：US12013800B1

    公开(公告)日：2024-06-18

    申请号：US18209685

    申请日：2023-06-14

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman

    IPC分类号： G06F13/20 ,  G01R31/317

    CPC分类号： G06F13/20 ,  G01R31/31712 ,  G01R31/31725 ,  G06F2213/40

    摘要： An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.

    Memory device degradation monitoring
    8.
    发明授权
    Memory device degradation monitoring 有权

    公开(公告)号：US11929131B2

    公开(公告)日：2024-03-12

    申请号：US17782146

    申请日：2020-12-03

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman

    IPC分类号： G11C11/419 ,  G11C29/08

    CPC分类号： G11C29/08 ,  G11C11/419

    摘要： A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.

    Die-to-die connectivity monitoring
    9.
    发明授权
    Die-to-die connectivity monitoring 有权

    公开(公告)号：US11293977B2

    公开(公告)日：2022-04-05

    申请号：US17205780

    申请日：2021-03-18

    申请人： proteanTecs Ltd.

    发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman ,  Ishai Zeev Cohen ,  Shaked Rahamim ,  Alex Khazin

    IPC分类号： G01R31/10 ,  H01L23/538 ,  H03K19/003 ,  G01R31/3173 ,  G01R31/30

    摘要： An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

    Efficient integrated circuit simulation and testing
    10.
    发明授权
    Efficient integrated circuit simulation and testing 有权

    公开(公告)号：US11132485B2

    公开(公告)日：2021-09-28

    申请号：US17254468

    申请日：2019-06-19

    申请人： PROTEANTECS LTD.

    发明人： Evelyn Landman ,  Yair Talker ,  Eyal Fayneh ,  Yahel David ,  Shai Cohen ,  Inbar Weintrob

    IPC分类号： G06F30/30 ,  G06F30/3312 ,  G06F111/08 ,  G06F119/22 ,  G06F119/06

    摘要： A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.