公开(公告)号：US09236287B2

公开(公告)日：2016-01-12

申请号：US13667389

申请日：2012-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Solomon Assefa ,  William M. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/0274 ,  H01L21/76232 ,  H01L21/76281 ,  H01L21/76283

Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Abstract translation: 通过在通过沟槽隔离工艺或通过热氧化产生的局部掩埋氧化物上沉积的非晶体半导体层的横向外延形成光子学SOI器件。 具体地说，并且在将半导体衬底形成沟槽之后，可以通过沉积工艺填充沟槽，或者可以进行热氧化以在半导体衬底内形成局部掩埋氧化物。 在一些实施例中，氧化物可以凹入以暴露半导体衬底的侧壁表面。 接下来，形成非晶半导体层，然后进行形成局部绝缘体上半导体层的固态结晶。 在固态结晶处理期间，非晶半导体层的与衬底的暴露的侧壁表面相邻的部分结晶。

公开(公告)号：US20150294976A1

公开(公告)日：2015-10-15

申请号：US14250064

申请日：2014-04-10

Applicant: GLOBALFOUNDIES INC.

Inventor： Ryan Ryoung-Han Kim ,  Youngtag Woo

IPC: H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L27/1104 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/1116 ,  H01L29/6656

Abstract: In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer.

Abstract translation: 在一个示例中，该方法包括执行至少一个处理操作以在衬底的第一区域中形成第一多个活动鳍片和至少一个牺牲鳍片，同时在所述衬底的第二区域中仅形成第二多个活动鳍片 ，形成覆盖所述第一和第二区域中的所有活性鳍片的翅片去除掩模层，并且在所述第一区域中暴露所述至少一个牺牲鳍片，其中所述翅片移除掩模层处于适当位置，执行至少一个蚀刻工艺 去除第一区域中的至少一个牺牲翅片并去除翅片移除掩模层。

公开(公告)号：US08723321B2

公开(公告)日：2014-05-13

申请号：US11448788

申请日：2006-06-08

Applicant: Christy Woo ,  Jun “Charlie” Zhai ,  Paul Besser ,  Kok-Yong Yiang ,  Richard C. Blish ,  Christine Hau-Riege

Inventor： Christy Woo ,  Jun “Charlie” Zhai ,  Paul Besser ,  Kok-Yong Yiang ,  Richard C. Blish ,  Christine Hau-Riege

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract translation: 通过图案化之后Cu线和其上的覆盖层之间的剥离应力通过改变通孔的形状并定位通孔来减小，以增加通孔和线边缘之间的空间，从而增加电迁移寿命。 实施例包括改变通孔的形状，如通过形成椭圆形或矩形形状的通孔，使得椭圆形的短轴与线之间的比例或矩形的宽度与线宽的比率小于 约0.7。