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    Method of forming a metal gate structure with tuning of work function by silicon incorporation
    3.
    发明授权
    Method of forming a metal gate structure with tuning of work function by silicon incorporation 有权
    通过硅掺入调整功函数形成金属栅结构的方法

    公开(公告)号：US07071086B2

    公开(公告)日：2006-07-04

    申请号：US10420721

    申请日：2003-04-23

    申请人： Christy Woo ,  Paul Besser ,  Minh van Ngo ,  James Pan ,  Jinsong Yin

    发明人： Christy Woo ,  Paul Besser ,  Minh van Ngo ,  James Pan ,  Jinsong Yin

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3215 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/78

    摘要： A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

    摘要翻译： 用于形成具有受控功函数的金属栅极的半导体结构的方法包括形成具有基板的前体的步骤，该基板具有被沟道分隔的有源区，在该沟道上的介电层内的临时栅极。 移除临时栅极以形成具有介电层中的底部和侧壁的凹部。 在凹槽中沉积非硅的金属层。 将硅结合到金属层中，并且在金属层上沉积金属。 通过在沉积金属层之前，之后或之后进行的硅烷处理来实现硅的引入。 结合到金属层中的硅的量控制形成的金属栅的功函数。

    Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric
    4.
    发明授权
    Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric 有权
    具有金属栅极和高k钽氧化物或氮氧化钽栅极电介质的半导体器件

    公开(公告)号：US07060571B1

    公开(公告)日：2006-06-13

    申请号：US10777138

    申请日：2004-02-13

    申请人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

    发明人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

    摘要翻译： 微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化 在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。 或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极 电介质层。

    Dual-level stacked flash memory cell with a MOSFET storage transistor
    5.
    发明申请
    Dual-level stacked flash memory cell with a MOSFET storage transistor 有权
    具有MOSFET存储晶体管的双电平堆叠闪存单元

    公开(公告)号：US20050232051A1

    公开(公告)日：2005-10-20

    申请号：US11154070

    申请日：2005-06-16

    申请人： James Pan ,  Ning Chen ,  Christy Woo

    发明人： James Pan ,  Ning Chen ,  Christy Woo

    IPC分类号： G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792

    CPC分类号： H01L21/28273 ,  G11C16/0475 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7923

    摘要： The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

    摘要翻译： 本发明是一种双电平闪存单元设计，其存储每个晶体管3个或更多位的信息。 双级存储器单元存储第一级中的两个较低位，并将高位存储在第二级。 低位通过可选的工作模式进行编程，擦除和读取，其中有源区域作为源极和漏极，然后漏极和源极工作。 高位被编程和擦除，独立于低位。 然而，读取较高位取决于较低位的读取值。 采用附加级别来存储超过3位的信息。

    Method for preventing an increase in contact hole width during contact formation
    6.
    发明申请
    Method for preventing an increase in contact hole width during contact formation 失效
    防止接触形成时接触孔宽度增大的方法

    公开(公告)号：US20050101148A1

    公开(公告)日：2005-05-12

    申请号：US10705631

    申请日：2003-11-08

    申请人： Dawn Hopper ,  Hiroyuki Kinoshita ,  Christy Woo

    发明人： Dawn Hopper ,  Hiroyuki Kinoshita ,  Christy Woo

    IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76865

    摘要： According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

    摘要翻译： 根据一个示例性实施例，用于在位于半导体管芯中的硅化物层上形成接触的方法包括在接触孔的侧壁和位于接触孔的底部的自然氧化物层上沉积阻挡层的步骤， 其中侧壁由电介质层中的接触孔限定。 可以优化将阻挡层沉积在接触孔的侧壁和自然氧化物层上的步骤，使得阻挡层在接触孔的顶部具有比接触孔底部的厚度更大的厚度。 根据该示例性实施例，该方法还包括去除位于接触孔底部的阻挡层和自然氧化物层的一部分以露出硅化物层的步骤。

    Use of ta/tan for preventing copper contamination of low-k dielectric layers
    8.
    发明授权
    Use of ta/tan for preventing copper contamination of low-k dielectric layers 有权
    使用ta / tan来防止低k电介质层的铜污染

    公开(公告)号：US06663787B1

    公开(公告)日：2003-12-16

    申请号：US09776747

    申请日：2001-02-06

    申请人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

    发明人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76862 ,  H01L21/76865

    摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，电介质层和延伸穿过介电层的开口，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 开口也可以有圆角。 侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由不同于第一阻挡层的材料形成，并且第一阻挡层的材料可以选自钽，钛，氮化钽，氮化钛和氮化钨。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 还公开了制造半导体器件的方法。

    Dual damascene integration scheme for preventing copper contamination of dielectric layer
    9.
    发明授权
    Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
    用于防止介电层铜污染的双镶嵌一体化方案

    公开(公告)号：US06586842B1

    公开(公告)日：2003-07-01

    申请号：US09793993

    申请日：2001-02-28

    申请人： Lu You ,  Fei Wang ,  Christy Woo

    发明人： Lu You ,  Fei Wang ,  Christy Woo

    IPC分类号： H01L2352

    CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。