公开(公告)号：US07064973B2

公开(公告)日：2006-06-20

申请号：US10857667

申请日：2004-05-28

申请人： Jack Zezhong Peng ,  Zhongshang Liu ,  David Fong ,  Fei Ye

发明人： Jack Zezhong Peng ,  Zhongshang Liu ,  David Fong ,  Fei Ye

IPC分类号： G11C11/24

CPC分类号： G11C11/405 ,  G11C11/406 ,  G11C17/16 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11807 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/1778

摘要： A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

摘要翻译： 公开了可用作用于存储用于编程现场可编程门阵列（FPGA）的数据的动态存储单元的单元。 该单元包括具有栅极，源极和漏极的选择晶体管，栅极连接到所述写位线，源极连接到浮点节点，漏极连接到行字线。 感测装置确定存储在浮点节点上的数据。 最后提供由浮点节点控制的开关。

公开(公告)号：US20060033528A1

公开(公告)日：2006-02-16

申请号：US11252126

申请日：2005-10-17

申请人： Man Wang

发明人： Man Wang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728

摘要： A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.

公开(公告)号：US20070176644A1

公开(公告)日：2007-08-02

申请号：US11400924

申请日：2006-04-10

申请人： Donghui Li ,  Jack Peng ,  Jason Chen

发明人： Donghui Li ,  Jack Peng ,  Jason Chen

IPC分类号： H03K19/094

CPC分类号： H03K19/0948

摘要： Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

摘要翻译： 公开了实现可编程逻辑发生器的方法和装置，其提供兼容查找表（LUT）的优点，同时为相同数量的功能利用较少的硅空间和功率。 所公开的方法和装置使用可编程开关来模拟在LUT中使用的存储器单元，并且示出了将2-和3-输入LUT的构造作为其他多输入LUT的构造块。

公开(公告)号：US07193436B2

公开(公告)日：2007-03-20

申请号：US11108927

申请日：2005-04-18

申请人： Man Wang ,  Suhail Zain

发明人： Man Wang ,  Suhail Zain

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.

摘要翻译： 所描述的实施例涉及现场可编程门阵列（FPGA）的一般区域，尤其涉及FPGA的构建块的架构和结构。 建议的逻辑单元，作为主要由查找表，多路复用器和锁存器组成的单独单元或单元链，实现不同的数学和逻辑功能。 具有两个输出，逻辑单元的实施例可以以分割模式操作，并且同时执行两个单独的逻辑和/或算术功能。 所提出的逻辑单元的链路，其中每隔一个单元由两个半个时钟周期中的一个计时，并利用局部互连而不是传统的路由信道，增加效率和速度，并减少所需的房地产。

公开(公告)号：US07277348B2

公开(公告)日：2007-10-02

申请号：US11356805

申请日：2006-02-17

申请人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

发明人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C2216/26

摘要： Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

摘要翻译： 存储单元包括SRAM和OTP存储器单元，其结合了两种技术的优点，并且可以通过标准CMOS制造制造而不需要额外的掩蔽。 概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，存储器单元的SRAM部分允许对单元进行无数次的编程，这在原型设计中是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

公开(公告)号：US20070133334A1

公开(公告)日：2007-06-14

申请号：US11356805

申请日：2006-02-17

申请人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

发明人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C2216/26

摘要： Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

摘要翻译： 公开了包括SRAM和OTP存储器单元的存储器单元，其结合了这两种技术的优点，并且可以通过标准CMOS制造来制造而不需要额外的掩蔽。 公开的概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，所公开的存储单元的SRAM部分允许对单元进行无数次编程，这在例如原型设计期间是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

公开(公告)号：US07061275B2

公开(公告)日：2006-06-13

申请号：US11252126

申请日：2005-10-17

申请人： Man Wang

发明人： Man Wang

IPC分类号： H03K19/094 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728

摘要： A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.

摘要翻译： 公开了一种具有分层互连结构的现场可编程门阵列（FPGA）。 FPGA包括通过互连结构在其间路由信号的逻辑头。 每个逻辑头包括可执行组合逻辑的多个级联逻辑块。 逻辑头可以进一步破碎成两个独立的逻辑单元。

公开(公告)号：US07411424B2

公开(公告)日：2008-08-12

申请号：US11400924

申请日：2006-04-10

申请人： Donghui Li ,  Jack Zezhong Peng ,  Jason Chen

发明人： Donghui Li ,  Jack Zezhong Peng ,  Jason Chen

IPC分类号： H03K19/20

CPC分类号： H03K19/0948

摘要： Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

摘要翻译： 公开了实现可编程逻辑发生器的方法和装置，其提供兼容查找表（LUT）的优点，同时为相同数量的功能利用较少的硅空间和功率。 所公开的方法和装置使用可编程开关来模拟在LUT中使用的存储器单元，并且示出了将2-和3-输入LUT的构造作为其他多输入LUT的构造块。

公开(公告)号：US07164290B2

公开(公告)日：2007-01-16

申请号：US10974107

申请日：2004-10-26

申请人： Guy Schlacter

发明人： Guy Schlacter

IPC分类号： H03K19/177 ,  G06F7/42

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

摘要翻译： 本发明的实施例涉及现场可编程门阵列的一般区域，特别涉及现场可编程门阵列的结构单元的架构和结构。 所提出的逻辑单元，作为主要由查找表，多路复用器和锁存器组成的分离单元或单元组，实现加法，减法，乘法等功能，并且可以作为移位寄存器，有限状态机， 多路复用器，累加器，计数器，多级随机逻辑和查找表等功能。 具有两个输出，逻辑单元的实施例可以在分离模式下操作并且同时执行两个单独的逻辑和/或算术功能。 所提出的逻辑单元的集群利用局部互连而不是传统的路由信道来增加效率，速度和减少所需的房地产。

公开(公告)号：US07135886B2

公开(公告)日：2006-11-14

申请号：US10944978

申请日：2004-09-20

申请人： Guy Schlacter

发明人： Guy Schlacter

IPC分类号： H03K19/173 ,  G11C7/00

CPC分类号： H03K19/17772 ,  G11C14/00 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/1778 ,  H03K19/17784

摘要： The embodiments of the present invention relate to the general area of Field Programmable Gate Arrays and, in particular, to Field Programmable Gate Arrays (“FPGAs”) comprising memory cells with both volatile and nonvolatile properties, and the control and management of each portion to overcome the disadvantages of each individual technology. Some of the advantages of combining the two properties in a single FPGA are power reduction, shorter power-on time, configuration flexibility, instant-on logic capability, cost savings in system components including nonvolatile instant-on devices, configuration memories, and standard CMOS process. Furthermore, to optimize these and other advantages of the proposed architecture, additional apparatus and methods are presented to individually and collectively manage and control different parts of such hybrid FPGAs.

摘要翻译： 本发明的实施例涉及现场可编程门阵列的一般领域，特别涉及包括具有易失性和非易失性特性的存储器单元的现场可编程门阵列（“FPGA”），以及每个部分的控制和管理 克服每个技术的缺点。 在单个FPGA中组合两个特性的一些优点是功耗降低，上电时间更短，配置灵活性，即时逻辑功能，系统组件中的成本节省，包括非易失性即插即用设备，配置存储器和标准CMOS 处理。 此外，为了优化所提出的架构的这些和其他优点，提出了附加的装置和方法以单独和集体地管理和控制这种混合FPGA的不同部分。