公开(公告)号：US10783292B1

公开(公告)日：2020-09-22

申请号：US15162458

申请日：2016-05-23

申请人： Pulsic Limited

发明人： Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F17/50 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F111/12

摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

公开(公告)号：US10769343B2

公开(公告)日：2020-09-08

申请号：US16506970

申请日：2019-07-09

申请人： Pulsic Limited

发明人： Jeremy Birch

IPC分类号： G06F30/394

摘要： A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

公开(公告)号：US09940421B1

公开(公告)日：2018-04-10

申请号：US13270085

申请日：2011-10-10

申请人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

发明人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F17/50 ,  G06F9/455 ,  G09G3/20

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G09G3/2088

摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on a random normalized polish expression, and includes cost considerations based on routing of interconnect.

公开(公告)号：US08949760B2

公开(公告)日：2015-02-03

申请号：US13346491

申请日：2012-01-09

申请人： Jeremy Birch ,  Mark Waller ,  Graham Balsdon

发明人： Jeremy Birch ,  Mark Waller ,  Graham Balsdon

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.

摘要翻译： 一种技术将自动路由集成电路的互连，并调整磁道或互连之间的间距，以提高性能或减少电迁移效应。 通过增加某些轨道或移动轨道之间的间距，性能可以提高，因为轨道将在相同层或不同层上的附近轨道具有更高的抗噪声能力。 自动路由器将根据一个或多个因素来调整轨道之间的间距。 这些因素可以包括与轨道相关的电流，轨道的宽度，电容，电感和电迁移。 在具体实现中，该技术使用基于形状的方法，其中不使用网格。 该技术可以进一步改变轨道的宽度。

公开(公告)号：US08010928B1

公开(公告)日：2011-08-30

申请号：US12048948

申请日：2008-03-14

申请人： Jeremy Birch ,  Mark Waller ,  Mark Williams ,  Graham Balsdon ,  Fumiaki Sato ,  Tim Parker

发明人： Jeremy Birch ,  Mark Waller ,  Mark Williams ,  Graham Balsdon ,  Fumiaki Sato ,  Tim Parker

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.

摘要翻译： 一种自动布线集成电路设计互连的系统，同时考虑到它所产生的布线的寄生问题。 该系统将能够选择合适的布线图案，使信号满足其性能要求。

公开(公告)号：US07823113B1

公开(公告)日：2010-10-26

申请号：US11530613

申请日：2006-09-11

申请人： Mark Waller ,  Tim Parker ,  Mark Williams ,  Jeremy Birch ,  Graham Balsdon ,  Fumiako Sato

发明人： Mark Waller ,  Tim Parker ,  Mark Williams ,  Jeremy Birch ,  Graham Balsdon ,  Fumiako Sato

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

摘要翻译： 提供提供改进的路由质量的集成电路的互连路由的方法和技术。 在本发明的一个实施例中，该技术提供线性脊柱互连路由。 在诸如DRAM和SRAM存储器设计的存储器阵列块中，连接的引脚通常在第一方向上分开大距离，在第二方向或脊柱或通道区域上分开小距离。 在脊椎区域内定义路线区域。 在一个实施例中，识别路线区域中的障碍物并且划定对应的禁止区域。 线性脊线互连在路线区域内沿第一方向路由，同时避免禁止区域。 引脚通过缝合互连连接到脊柱互连。 缝合互连通常沿第二方向布线。

公开(公告)号：US07784010B1

公开(公告)日：2010-08-24

申请号：US10709844

申请日：2004-06-01

申请人： Graham Balsdon ,  Jeremy Birch ,  Mark Williams ,  Mark Waller ,  Tim Parker ,  Fumiaki Sato

发明人： Graham Balsdon ,  Jeremy Birch ,  Mark Williams ,  Mark Waller ,  Tim Parker ,  Fumiaki Sato

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/78

摘要： A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.

摘要翻译： 系统使用可变宽度的互连线路自动路由集成电路设计的互连。 例如，第一自动路由互连可以具有与第二自动路由互连不同的宽度。 系统将根据某些因素或标准改变互连线的宽度。 这些因素包括电流或功率处理，可靠性，电迁移，电压降，自热，光学邻近效应或其他因素，或这些因素的组合。 该系统可以使用网格或无网格（或基于形状的）方法。

公开(公告)号：US07657852B2

公开(公告)日：2010-02-02

申请号：US11275726

申请日：2006-01-25

申请人： Mark Waller

发明人： Mark Waller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.

摘要翻译： 一种用于指定在集成电路布局中搜索的模式并指定所提出的替换模式的系统和技术。 描述文件包括要搜索的一个或多个模式的规范。 在描述文件中，对于每个模式，可以存在一个或多个所提出的替换模式。 描述文件被读取。 找到布局中的模式匹配（如果有）。 测试提出的替换图案来代替匹配的图案。 如果可以接受，则可以使用所提出的模式来替换匹配的模式。

公开(公告)号：US07257797B1

公开(公告)日：2007-08-14

申请号：US10908895

申请日：2005-05-31

申请人： Mark Waller ,  Tim Parker ,  Mark Williams ,  Jeremy Birch ,  Graham Balsdon ,  Fumiaki Sato

发明人： Mark Waller ,  Tim Parker ,  Mark Williams ,  Jeremy Birch ,  Graham Balsdon ,  Fumiaki Sato

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

摘要翻译： 提供提供改进的路由质量的集成电路的互连路由的方法和技术。 在本发明的一个实施例中，该技术提供线性脊柱互连路由。 在诸如DRAM和SRAM存储器设计的存储器阵列块中，连接的引脚通常在第一方向上分开大距离，在第二方向或脊柱或通道区域上分开小距离。 在脊椎区域内定义路线区域。 在一个实施例中，识别路线区域中的障碍物并且划定对应的禁止区域。 线性脊线互连在路线区域内沿第一方向路由，同时避免禁止区域。 引脚通过缝合互连连接到脊柱互连。 缝合互连通常沿第二方向布线。

公开(公告)号：US20060288323A1

公开(公告)日：2006-12-21

申请号：US11425504

申请日：2006-06-21

申请人： Jeremy Birch

发明人： Jeremy Birch

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  Y02A10/46

摘要： A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

摘要翻译： 基于高速形状的路由器适用于标准单元数字设计，芯片级块装配设计和其他设计风格。 在本发明的流程中，该技术为要路由的每个网络建立初始结构。 网或其中的一部分被订购。 网络的每个部分可以使用脊线路由搜索，深度优先搜索或空间洪泛搜索或这些的任何组合来路由。 在哪些部分出现故障或发生错误的情况下，会发现冲突，并且技术再次尝试路由。