公开(公告)号：US08145469B2

公开(公告)日：2012-03-27

申请号：US12426164

申请日：2009-04-17

Applicant: Alexandre Birguer

Inventor： Alexandre Birguer

IPC: G06F9/455

CPC classification number: G06F12/1072 ,  G06F9/45537 ,  G06F17/5027

Abstract: A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.

Abstract translation: 用于紧凑地映射不同存储器系统的存储器映射系统及其制造和使用方法。 映射系统通过划分源存储器系统并将分区源存储器系统内的存储器内容分配到目的地存储器系统中来将源存储器系统映射到目的地存储器系统。 在一个实施例中，映射系统根据目的地存储器系统的目的地数据宽度来分解源存储器系统的源数据宽度，以形成至少一个数据子宽度。 为每个数据子宽度定义源存储器子区域。 与每个源存储器子区域相关联的存储器内容以目的地存储器系统的所选目的地存储器寄存器并排的方式设置在目的地存储器系统内。 因此，映射系统可以将存储器内容紧凑地映射到目的地存储器系统中，而不会损失有价值的存储器空间。

公开(公告)号：US07738398B2

公开(公告)日：2010-06-15

申请号：US10992165

申请日：2004-11-17

Applicant: Barton L. Quayle ,  Mitchell G. Poplack ,  Peter Tannenbaum

Inventor： Barton L. Quayle ,  Mitchell G. Poplack ,  Peter Tannenbaum

IPC: H04L12/28

CPC classification number: G06F17/5027 ,  H04L25/0272

Abstract: An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.

Abstract translation: 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。

公开(公告)号：US07555424B2

公开(公告)日：2009-06-30

申请号：US11377762

申请日：2006-03-16

Applicant: Alon Kfir ,  Platon Beletsky

Inventor： Alon Kfir ,  Platon Beletsky

IPC: G06F9/455 ,  G06F11/16

CPC classification number: G06F17/5022

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract translation: 用于在逻辑仿真系统中仿真存储器电路的方法和装置，包括计算机程序产品。 该系统包括与仿真存储器相关联的至少一个日志存储器。 每个日志存储器位置在预定时间被标记为无效。 系统在预定时间之后接收一个或多个存储器写请求，每个存储器写请求指定要写入指定存储单元的新数据。 如果对应于指定的存储单元的日志存储器位置被标记为无效，则在写入新数据之前，将指定的存储器位置的预写内容复制到相应的日志存储器位置，并且相应的日志存储器位置被标记为有效 在模拟存储器中的指定存储器位置。 通过将标记为有效的每个日志存储器位置的内容复制到仿真存储器来将仿真存储器恢复到预定时间。

公开(公告)号：US07356455B2

公开(公告)日：2008-04-08

申请号：US10975676

申请日：2004-10-28

Applicant: Barton Quayle ,  Mitchell G. Poplack

Inventor： Barton Quayle ,  Mitchell G. Poplack

IPC: G06F9/455 ,  G06F17/50 ,  G06G7/62 ,  G06F11/00

CPC classification number: G06F17/5027 ,  G06F17/5022 ,  G06F2217/86

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract translation: 公开了一种用于仿真系统和仿真器之间的仿真和可视化数据传输的优化接口。 在一个实施例中，一种在仿真器之间通过接口传送数据的方法包括更新模拟器的模拟器缓冲器以包含用于仿真周期的期望的输入状态。 执行对该接口的目标写入，以指示仿真循环可以继续进行。 使用独立于模拟器的接口内的指令序列器来完成仿真周期。

公开(公告)号：US07257524B2

公开(公告)日：2007-08-14

申请号：US10247186

申请日：2002-09-18

Applicant: William John Schilp ,  Pramodini Arramreddy ,  Krishna Babu Bangera ,  Makarand Yashwant Joshi

Inventor： William John Schilp ,  Pramodini Arramreddy ,  Krishna Babu Bangera ,  Makarand Yashwant Joshi

IPC: G06F17/50 ,  G06G7/62 ,  G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F9/455

CPC classification number: G06F17/5022

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract translation: 完全可综合仿真控制模块（SCM）可以对被测设计（DUT）的仿真进行控制和监控。 SCM内的时钟发生器和驻留在主机工作站上的软件时钟设备负责为DUT提供时钟。 SCM和硬件时钟设备在构建时动态生成，以满足DUT的需要。 它们通过为包含多个异步时钟的设计自动生成时钟波形来最大限度地提高性能，从而降低加速器 - 工作站交互的频率。 软件时钟设备能够直接驱动DUT，并负责管理仿真时间和时钟参数。 SCM还负责监视中止条件，例如执行外部软件模型的触发器。 SCM和时钟设备允许硬件加速器有效地支持多个异步时钟域，执行外部软件模型和协同仿真。

公开(公告)号：US07054802B2

公开(公告)日：2006-05-30

申请号：US09879658

申请日：2001-06-11

Applicant: Takahide Ohkami

Inventor： Takahide Ohkami

IPC: G06F17/50 ,  G06F11/00

CPC classification number: G06F17/5022

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract translation: 提供了一种系统，用于在硬件辅助设计验证系统中进行功能验证的用户设计中增加寄存器和存储器的可访问性。 在逻辑模拟期间，基于分组的协议用于在主机工作站和硬件加速器之间执行数据传输操作，用于在目标设计（DUV）期间将数据加载到数据和从寄存器和存储器中卸载数据。 该方法和装置将接口逻辑合成到DUV中以提供对在硬件加速器的辅助下模拟的目标DUV中的寄存器和存储器的更大访问。

公开(公告)号：US07043417B1

公开(公告)日：2006-05-09

申请号：US09656146

申请日：2000-09-06

Applicant: William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

Inventor： William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

IPC: G06F9/455 ,  G06F13/00

CPC classification number: G06F13/1647

Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

Abstract translation: 在仿真器处理器集群中，共享输入和数据存储器堆栈的读取端口被时间复用以服务于多个处理器。 在本发明的示例性实施例中，256x8存储器阵列用作簇中四个处理器的共享存储器。 两个读端口在集群中的四个处理器之间进行时间复用。 在一个读取周期中，来自两个读取端口的数据耦合到两个处理器。 下一个读取周期将数据从相同的两个端口读取到剩余的两个处理器。 在优选实施例中，存储器以系统时钟速度的两倍运行，使得整体仿真处理执行时间不受影响。

公开(公告)号：US20050278163A1

公开(公告)日：2005-12-15

申请号：US11141141

申请日：2005-05-31

Applicant: Mitchell Poplack ,  John Maher

Inventor： Mitchell Poplack ,  John Maher

IPC: G06F9/455

CPC classification number: G06F11/261

Abstract: A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.

Abstract translation: 一种用于连接通信系统的选定组件的信号转换系统及其制造和使用方法。 信号转换系统将所选逻辑信号从一个系统组件转换成一对差分逻辑信号，并将一对差分逻辑信号提供给第二系统组件，以解决任何逻辑和/或时间假象。 当所选逻辑信号中的一个或多个改变信号状态时，信号转换系统将该对差分逻辑信号维持在第一有效组合信号状态，直到所选逻辑信号的信号状态对应于第二有效组合信号状态 差分逻辑信号对。 信号验证系统然后更新该对差分逻辑信号以具有第二有效组合信号状态。 因此，系统组件可以通信，交换差分通信信号，同时保持占空比并避免信令故障。

公开(公告)号：US20050266709A1

公开(公告)日：2005-12-01

申请号：US11062047

申请日：2005-02-18

Applicant: Catalino Datan ,  Mitchell Poplack

Inventor： Catalino Datan ,  Mitchell Poplack

IPC: H01R13/62 ,  H01R13/633

CPC classification number: H01R12/7005

Abstract: A mechanism is described for effecting the ejection of a high extraction force electromechanical connector from its mate by utilizing an ejector mechanism and without requiring custom design or manufacturing of the mating connector. One embodiment achieves this by way of rigid sliding frame which applies force to a portion of the mating connector which is otherwise intended to provide alignment guidance between the two connectors.

Abstract translation: 描述了一种机构，用于通过利用喷射器机构实现高吸力机电连接器的喷射，而不需要定制设计或配制连接器的制造。 一个实施例通过刚性滑动框架来实现，该刚性滑动框架对配合连接器的一部分施加力，否则其旨在在两个连接器之间提供对准引导。

公开(公告)号：US20020107682A1

公开(公告)日：2002-08-08

申请号：US10107741

申请日：2002-03-26

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

IPC: G06F009/455

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract translation: 用于电子电路或系统的物理仿真的系统包括数据输入工作站，其中用户可以输入表示电路或系统配置的数据。 该数据被转换成适合于编程具有丰富互连架构的可编程门元件阵列的形式。 规定用于外部连接VLSI设备或用户电路或系统的其他部分。 通过利用可编程门阵列中未使用的电路路径可以获得内部探测互连网络。