公开(公告)号：US4959618A

公开(公告)日：1990-09-25

申请号：US311216

申请日：1989-02-16

申请人： John S. Shier

发明人： John S. Shier

IPC分类号： H03L7/089

CPC分类号： H03L7/0896

摘要： A differential charge pump for use in a phase locked loop. The charge pump generates a voltage difference signal proportional to the duration of first and second pulse trains provided by a phase comparator. The charge pump includes a differential amplifier for generating the difference signal, first and second RC filter networks connected between the noninverting and inverting terminals of the differential amplifier and a reference node, respectively. Parallel, all-NPN switching networks apply charging current pulses to the first RC filter network in response to the first pulse train and they apply charging current pulses to the second RC filter network in response to the second pulse train.

摘要翻译： 用于锁相环的差动电荷泵。 电荷泵产生与由相位比较器提供的第一和第二脉冲串的持续时间成比例的电压差信号。 电荷泵包括用于产生差分信号的差分放大器，分别连接在差分放大器的非反相端和反相端之间的第一和第二RC滤波器网络以及参考节点。 平行的，全NPN交换网络响应于第一脉冲串将充电电流脉冲施加到第一RC滤波器网络，并且响应于第二脉冲串将充电电流脉冲施加到第二RC滤波器网络。

公开(公告)号：US4923824A

公开(公告)日：1990-05-08

申请号：US186555

申请日：1988-04-27

申请人： Daniel J. Fertig ,  Matthew F. Schmidt

发明人： Daniel J. Fertig ,  Matthew F. Schmidt

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/6659 ,  H01L29/7801 ,  H01L29/7836 ,  H01L29/1087

摘要： A lightly doped drain in an IGFET is provided by fabricating the transistor in a epitaxial layer lightly doped in the conductivity type of the channel for the device. The laterally reduced dopant concentration of the drain, and a lightly doped source if desired, is provided by leaving portions of the epitaxial layer unmodified.

摘要翻译： 通过在该器件的沟道的导电类型中轻掺杂的外延层中制造晶体管来提供IGFET中的轻掺杂漏极。 通过使外延层的部分未修改来提供漏极的横向减小的掺杂剂浓度和如果需要的轻掺杂源。

公开(公告)号：US4843342A

公开(公告)日：1989-06-27

申请号：US130526

申请日：1987-12-09

申请人： Richard E. Hester ,  Tuan V. Ngo

发明人： Richard E. Hester ,  Tuan V. Ngo

IPC分类号： H03F1/56 ,  H03F3/45

CPC分类号： H03F1/56 ,  H03F3/45071

摘要： A bias current cancellation circuit provides current to the bases of a pair of transistors forming a differential amplifier. A transistor of matched characteristics to the differential amplifier pair is operated so that its base current replicates the base currents of the differential transistor pair. This replicated base current is inverted by a current mirror which is connected to the bases of the differential transistional pair. A second order cancellation error caused by base current differences in the current mirror is cancelled by a feedback circuit so that only the base current of the matching transistor affects the currents supplied to differential amplifier.

摘要翻译： 偏置电流消除电路为形成差分放大器的一对晶体管的基极提供电流。 操作具有与差分放大器对的匹配特性的晶体管，使得其基极电流复制差分晶体管对的基极电流。 这个复制的基极电流被连接到差分转置对的基极的电流镜反转。 由电流镜中的基极电流差导致的二阶消除误差由反馈电路消除，使得只有匹配晶体管的基极电流才影响提供给差分放大器的电流。

公开(公告)号：US5134584A

公开(公告)日：1992-07-28

申请号：US223084

申请日：1988-07-22

申请人： Clifford H. Boler ,  Jeffrey A. Lukanc

发明人： Clifford H. Boler ,  Jeffrey A. Lukanc

IPC分类号： G11C29/00

CPC分类号： G11C29/848 ,  G11C29/88

摘要： A configurable device uses a plurality of parallel units which are made up of cells for storing individual bits of information. These cells are identified by address signals and selected to be interrogated. The selected cells are interrogated to determine information stored therein and a signal is produced which corresponds to that information. If a nonfunctional cell is detected within a parallel unit, that parallel unit may be decoupled from the interrogator. The remainder of the parallel units are shifted to different interrogators thereby effectively eliminating use of the decoupled parallel unit which contains the nonfunctional cell.

摘要翻译： 可配置的设备使用由小区组成的多个并行单元，用于存储信息的各个位。 这些单元由地址信号识别并选择进行询问。 所选择的单元被询问以确定存储在其中的信息，并产生对应于该信息的信号。 如果在并行单元内检测到非功能单元，则该并联单元可能与询问器分离。 剩余的并行单元被移动到不同的询问器，从而有效地消除了包含非功能单元的解耦并联单元的使用。

公开(公告)号：US4771228A

公开(公告)日：1988-09-13

申请号：US58770

申请日：1987-06-05

申请人： Richard E. Hester ,  Tuan Ngo

发明人： Richard E. Hester ,  Tuan Ngo

IPC分类号： G05F3/22 ,  G05F3/26

CPC分类号： G05F3/22

摘要： An amplifier output stage includes current limiting circuitry for limiting the current in the output stage if the output terminal is shorted to ground. The current sinking and the current sourcing output transistors each have a current limiting circuit which mirrors the collector current of the output transistor, produces a voltage which is a function of the mirrored collector current, and controls base current to the output transistor as a function of the voltage. The output current limiting function, therefore, is provided without sacrificing output voltage swing of the output stage.

摘要翻译： 放大器输出级包括限流电路，用于限制输出端的电流，如果输出端短接到地。 电流吸收和电流源输出晶体管各自具有电流限制电路，其反映输出晶体管的集电极电流，产生作为镜像集电极电流的函数的电压，并且控制作为输出晶体管的函数的基极电流 电压。 因此，在不牺牲输出级的输出电压摆幅的情况下提供输出限流功能。

公开(公告)号：US4885485A

公开(公告)日：1989-12-05

申请号：US238565

申请日：1988-08-30

申请人： William W. Leake ,  Rai Surinder

发明人： William W. Leake ,  Rai Surinder

IPC分类号： H01L27/118 ,  H03K17/12 ,  H03K17/16 ,  H03K17/687

CPC分类号： H03K17/164 ,  H01L27/11898 ,  H03K17/122 ,  H03K17/6872

摘要： A CMOS output buffer interconnects binary logic integrated circuits. The output buffer is readily configurable through variation of a single metallization mask during fabrication for providing interconnection of integrated circuits through either transmission lines or lumped loads. The CMOS output buffer provides a pull-up circuit for pulling an output terminal to a voltage level corresponding to a first logical state and a pull-down circuit for pulling the output terminal to the complementary logical state. The pull-up and pull-down circuits each include a plurality of parallel connectable output drivers. A selected number of output drivers can be connected to the output terminal during fabrication of the integrated circuit through the appropriate metallization mask. The pull-up and pull-down circuits each include a distributed, continuous control electrode providing for delayed propagation of actuation signals. Selective metallization between points of a control electrode prescribes different time rates of propagation of an actuation signal.

摘要翻译： CMOS输出缓冲器互连二进制逻辑集成电路。 输出缓冲器可以通过在制造期间通过改变单个金属化掩模进行配置，以通过传输线或集总负载提供集成电路的互连。 CMOS输出缓冲器提供用于将输出端拉至与第一逻辑状态相对应的电压电平的上拉电路和用于将输出端拉至互补逻辑状态的下拉电路。 上拉和下拉电路各自包括多个可并行连接的输出驱动器。 在通过合适的金属化掩模制造集成电路期间，所选数量的输出驱动器可连接到输出端。 上拉和下拉电路各自包括分布式连续的控制电极，其提供致动信号的延迟传播。 控制电极的点之间的选择性金属化规定了致动信号的不同传播时间速率。

公开(公告)号：US4851838A

公开(公告)日：1989-07-25

申请号：US134758

申请日：1987-12-18

申请人： John S. Shier

发明人： John S. Shier

IPC分类号： H03M1/00

CPC分类号： H03M1/1071 ,  H03M1/40 ,  H03M1/46 ,  H03M1/74

摘要： A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

摘要翻译： 单芯片单片集成逐次逼近模数转换器包括用于接收移位寄存器测试模式控制信号和逐次逼近模式控制信号的测试模式端子。 数字测试数据信号被应用于测试数据终端。 连接可调整的数模转换器（DAC）以接收数字信号，并将这些信号转换成相应值的模拟信号。 逐次逼近和移位寄存器耦合到测试模式终端和测试数据终端。 在后制造处理中，逐次逼近和移位寄存器响应于测试模式控制信号在移位寄存器测试模式下操作。 已知值的测试信号被串行接收并与DAC并行应用。 然后可以将DAC修剪为所需规格。 逐次逼近和移位寄存器响应于逐次逼近模式控制信号以逐次逼近模式工作。

公开(公告)号：US4964117A

公开(公告)日：1990-10-16

申请号：US253059

申请日：1988-10-04

申请人： John S. Shier

发明人： John S. Shier

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/033 ,  H04L7/0083

摘要： A timing synchronizing circuit with a phase locked loop. A multiplexor is employed to cause the phase locked loop to alternate between a self-excited mode for maintaining the frequency of a recovered timing signal and a mode in which state transitions of a baseband data signal are compared with the phase locked loop feedback signal to adjust the frequency of the recovered timing signal.

摘要翻译： 具有锁相环的定时同步电路。 采用多路复用器使锁相环在自激模式之间交替，用于维持恢复的定时信号的频率和将基带数据信号的状态转换与锁相环反馈信号进行比较的模式进行调整 恢复的定时信号的频率。

公开(公告)号：US4868425A

公开(公告)日：1989-09-19

申请号：US129720

申请日：1987-12-07

申请人： Timothy M. Lindenfelser

发明人： Timothy M. Lindenfelser

IPC分类号： H03K19/003

CPC分类号： H03K19/00323

摘要： A skew compensated RS422 buffer includes a skew compensation circuit and an output driver. The output driver is connected to receive a complementary pair of compensated drive signals, and provides complementary buffer output signals in response thereto. Due to asymmetric switching characteristics, buffer output signals in response to falling edge drive signals are delayed by an inherent skew period with respect to buffer output signals in response to rising edge drive signals. The skew compensation circuit includes a NOR gate and an AND gate, both of which have a first input terminal connected to receive buffer input signals. The buffer input signals are also applied to second input terminals of both the NOR gate and AND gate through delay gates which delay signal propagation by delay periods substantially equal to the inherent skew period of the output driver. A complementary pair of compensated drive signals are provided at output terminals of the NOR and AND gates, thereby compensating for the asymmetric switching characteristics of the output driver means.

摘要翻译： 偏斜补偿RS422缓冲器包括偏斜补偿电路和输出驱动器。 输出驱动器被连接以接收互补的补偿驱动信号对，并响应于此提供互补的缓冲器输出信号。 由于不对称的开关特性，响应于下降沿驱动信号的缓冲器输出信号响应于上升沿驱动信号被延迟相对于缓冲器输出信号的固有偏斜周期。 偏斜补偿电路包括NOR门和AND门，它们都具有连接到接收缓冲器输入信号的第一输入端。 缓冲器输入信号还通过延迟门施加到或非门和与门的第二输入端，延迟门延迟信号传播延迟周期，基本上等于输出驱动器的固有偏斜周期。 在NOR和AND门的输出端提供一对互补的补偿驱动信号，从而补偿输出驱动器装置的非对称开关特性。

公开(公告)号：US4827222A

公开(公告)日：1989-05-02

申请号：US131804

申请日：1987-12-11

申请人： Richard E. Hester ,  Tuan V. Ngo

发明人： Richard E. Hester ,  Tuan V. Ngo

IPC分类号： H01C17/23 ,  H03F3/45

CPC分类号： H03F3/45623 ,  H01C17/23 ,  H03F2203/45048

摘要： Trimming of input offset voltage of a diferential amplifier is provided by a pair of resistance networks which are connected to the emitters of a pair of current mirror transistors. By adjusting the resistances of the resistance networks, the adjustment currents flowing through the current mirror transistors are selected to cancel out the input offset voltage of the differential amplifier. Each resistance network includes a plurality of resistors connected in series with a low resistance shorting link connected in parallel with each of the plurality of resistances. The input offset voltage is trimmed by selectively cutting the shorting links with a two-phase measure and trim process.

摘要翻译： 通过连接到一对电流镜晶体管的发射极的一对电阻网络来提供差分放大器的输入失调电压的微调。 通过调整电阻网络的电阻，选择流过电流镜晶体管的调节电流来抵消差分放大器的输入偏移电压。 每个电阻网络包括与与多个电阻中的每一个平行连接的低电阻短路连杆串联连接的多个电阻器。 通过用两相测量和修整过程选择性地切割短路链路来修剪输入失调电压。