摘要:
The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.
摘要:
The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.
摘要:
A startup system using a boot code includes an external memory storing a boot code, a buffer connected to an external memory for storing the boot code transferred from the external memory, a DMA controller for commanding transfer of the boot code from the external memory to the buffer, and a mapping circuit connected to the buffer for mapping the boot code stored in the buffer onto a CPU. Accordingly, a flash ROM for storing the boot code may be eliminated, thereby reducing system cost.
摘要:
Disclosed is a coating method comprising the steps of applying a color coating composition, applying a coating composition containing a pigment capable of producing a metallic effect to the layer of the color coating composition and applying a clear coating composition to the layer of the pigment-containing coating composition, characterized in that the color coating composition is able to form a layer having a Munsell value of 0 to 6; that the pigment-containing coating composition contains an iron oxide pigment and a vehicle as main components, the iron oxide pigment being iron oxide particles which contain at least 80% by weight of .alpha.-iron oxide crystals and which are each coated with titanium dioxide; that about 90% by weight or more of the iron oxide pigment has a longitudinal size of about 30 .mu.m or less than 40% by weight or more of the pigment has a longitudinal size of about 5 to about 15 .mu.m; that the thickness of the pigment is about 1/10 to about 1/20 of the longitudinal size of the pigment; and that the amount of the pigment is about 0.1 to about 30 parts by weight per 100 parts by weight of the vehicle (as solids).
摘要:
A memory module is described having a memory array storing data, an ID information output circuit for outputting ID information for identifying memory modules, and output switching means for selectively switching between output from the memory array and output from the ID information output circuit, and output from the ID information output circuit will be selected instead of output from the memory array until the memory module is initially written after the power supply to the memory module has been started. This enables a memory module to be identified without having to add parts to a computer system unit or providing a ROM storing a specification or the like to the memory module.
摘要:
Wireless data communication method and apparatus using two electromagnetic signals having different polarizations. Codes related to relative values of the amplitudes of the two signals are generated in correspondence with data to be transmitted. The signals are modulated according to the codes using phase shift keying and amplitude shift keying. The amplitude shift keying modulates the two electromagnetic signals by changing the difference between their two amplitudes in accordance with data encodings. The two signals are transmitted to receiver, which decodes the phases and relative amplitudes to obtain the codes, and reproduces the data from the obtained codes.
摘要:
The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip 12 including a bus retry output part (40) for outputting a bus retry (BRTY) signal; a bus retry detection part (30) for determining whether a bus retry signal is input from the bridge chip 12; and a bus cycle controller (38) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part (32) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller (38) for executing that other process before re-starting the suspended bus cycle.
摘要:
A web transfer system is disclosed which comprises an endless belt which has a first surface which is elastic and which is structured and arranged to come into direct contact with a web in a press section and a second surface which is not in contact with the web. The endless belt has an inner core, which is located between the first surface and the second surface. The inner core is made from a material which is less elastic than the first surface. The web transfer system also comprises a hard roll and at least one pressure roll which presses the endless belt into direct contact against the hard roll. When the endless belt is pressed against the hard roll, it is deformed so as to doff the web from the hard roll directly and convey the web with the endless belt. No suction force is imposed on the endless belt.
摘要:
The present invention relates to a coating composition containing a colored aluminum pigment and a titanium oxide pigment, wherein in the case where a coating film formed from the coating composition is illuminated at 45 degrees with respect to the surface of the coating film, a ratio of lightness L* of light observed at 45 degrees with respect to specularly reflected light, relative to lightness L* of light observed at 110 degrees with respect to specularly reflected light is within a range of 1.00 to 1.50. The invention further relates to a method for forming a coating film, including steps of applying the above-described coating composition to a substrate; and further applying a clear coating composition thereto.
摘要:
A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit.