Efficient, high frequency, class A-B amplifier for translating low
voltage clock signal levels to CMOS logic levels
    1.
    发明授权
    Efficient, high frequency, class A-B amplifier for translating low voltage clock signal levels to CMOS logic levels 失效
    高效,高频率的A-B类放大器,用于将低电压时钟信号电平转换为CMOS逻辑电平

    公开(公告)号:US5568093A

    公开(公告)日:1996-10-22

    申请号:US443955

    申请日:1995-05-18

    申请人: Reuven Holzer

    发明人: Reuven Holzer

    IPC分类号: H03F1/02 H03F3/30 H03K5/02

    摘要: A power efficient class A-B amplifier provides 20 dB amplification for a low capacitive load such as a 40 to 80 MHz clock signal in a crystal oscillator circuit. The amplifier includes two bias-and-clamp circuits coupled between an input stage and the gates of an N-channel transistor and a P-channel transistor. The N-channel and P-channel transistors are connected in series between VCC and ground and form an output stage. The bias-and-clamp circuits bias the N-channel and P-channel transistors in weak inversion for maximum amplification and clamp an input voltage to increase noise immunity and reduce power use. In one embodiment, each bias-and-clamp circuit includes two pairs of series connected transistors. A first pair is connected in series with a constant current source and form current mirrors with a second pair of transistors. A node between transistors in the second pair is connected to the gate of a transistor in the output stage and to the input voltage. Transistors in the bias-and-clamp circuits have a conductivity type which matches the conductivity type of the transistor in the output stage which the bias-and-clamp circuit controls.

    摘要翻译: 功率有效的A-B类放大器为低电容负载提供20 dB放大,例如在晶体振荡器电路中的40至80 MHz时钟信号。 放大器包括耦合在输入级和N沟道晶体管和P沟道晶体管的栅极之间的两个偏置和钳位电路。 N沟道和P沟道晶体管串联在VCC和地之间并形成输出级。 偏置钳位电路在弱反转中偏置N沟道和P沟道晶体管,以实现最大放大,并钳位输入电压以增加抗噪声能力并减少功耗。 在一个实施例中,每个偏置和钳位电路包括两对串联连接的晶体管。 第一对与恒流源串联连接,并与第二对晶体管形成电流镜。 第二对中的晶体管之间的节点连接到输出级中的晶体管的栅极和输入电压。 偏置和钳位电路中的晶体管具有与偏置和钳位电路控制的输出级中的晶体管的导电类型相匹配的导电类型。

    High-linearity complementary amplifier
    2.
    发明授权
    High-linearity complementary amplifier 有权
    高线性互补放大器

    公开(公告)号:US07936217B2

    公开(公告)日:2011-05-03

    申请号:US11947570

    申请日:2007-11-29

    IPC分类号: H03F3/18

    摘要: A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

    摘要翻译: 互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压,其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。 可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化,随着输入电容的变化和PMOS晶体管的跨导变化 中等反转区。 互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。

    HIGH-LINEARITY COMPLEMENTARY AMPLIFIER
    3.
    发明申请
    HIGH-LINEARITY COMPLEMENTARY AMPLIFIER 有权
    高线性互补放大器

    公开(公告)号:US20090140812A1

    公开(公告)日:2009-06-04

    申请号:US11947570

    申请日:2007-11-29

    IPC分类号: H03F3/16

    摘要: A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

    摘要翻译: 互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压,其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。 可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化,随着输入电容的变化和PMOS晶体管的跨导变化 中等反转区。 互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。