公开(公告)号：US09800273B1

公开(公告)日：2017-10-24

申请号：US15446847

申请日：2017-03-01

Applicant: QUALCOMM Incorporated

Inventor： Sherif Abdelhalem ,  Bassel Hanafi ,  Hasnain Lakdawala

IPC: H04B1/16 ,  H03F3/19 ,  H04B1/04 ,  H03F3/195 ,  H03F3/24

CPC classification number: H04B1/0458 ,  H03F3/193 ,  H03F3/195 ,  H03F3/245 ,  H03F3/3022 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/165 ,  H03F2200/294 ,  H03F2200/357 ,  H03F2200/451 ,  H04B1/0475

Abstract: A device and method for amplifying signals is provided. The device can have an input to receive an input signal having a first desired signal on a first carrier, a second desired signal on a second carrier, and one or more interfering signals. The device can have a first carrier aggregation (CA) chain for use with the first desired signal and a second CA chain for use with the second desired signal. The first and second CA chains can be coupled to the input. The first and second CA chains can have a plurality of transconductance stages. Each of the transconductance stages can be configured as a high impedance stage or a low impedance stage. The transconductance stages can be selectively activated to incrementally adjust the transconductance, and therefore the input impedance, of each of the CA chains.

公开(公告)号：US08237507B1

公开(公告)日：2012-08-07

申请号：US13047444

申请日：2011-03-14

Applicant: Ahmad Mirzaei ,  Hooman Darabi

Inventor： Ahmad Mirzaei ,  Hooman Darabi

IPC: H03F3/04

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/72 ,  H03F2200/357 ,  H03F2203/45541 ,  H03F2203/7236

Abstract: Aspects of a method and system for transmitter linearization are provided. A signal may be amplified via one or more circuits comprising a first transistor having a first bias voltage applied to its gate via a resistor, and a second transistor having its source coupled to a first terminal of the resistor, its drain coupled to a second terminal of the resistor, and its gate coupled to a second bias voltage. The signal may be AC-coupled, via one or more capacitors, for example, to the gate of the first transistor. The first bias voltage and the second bias voltage may be such that the first transistor operates in the active region the second transistor operates in the subthreshold region. The effective channel width of the second transistor may be configurable during operation of the one or more circuits.

Abstract translation: 提供发射机线性化的方法和系统的方面。 信号可以经由一个或多个电路被放大，该电路包括经由电阻器施加到其栅极的第一偏置电压的第一晶体管，以及其源极耦合到电阻器的第一端子的第二晶体管，其漏极耦合到第二端子 并且其栅极耦合到第二偏置电压。 信号可以经由一个或多个电容器例如AC耦合到第一晶体管的栅极。 第一偏置电压和第二偏置电压可以使得第一晶体管在有源区域中工作，第二晶体管在亚阈值区域中工作。 在一个或多个电路的操作期间，第二晶体管的有效沟道宽度可以是可配置的。

公开(公告)号：US07746169B2

公开(公告)日：2010-06-29

申请号：US12027107

申请日：2008-02-06

Applicant: Junxiong Deng ,  Christian Holenstein ,  Namsoo Kim

Inventor： Junxiong Deng ,  Christian Holenstein ,  Namsoo Kim

IPC: H03F3/45

CPC classification number: H03F3/193 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45188 ,  H03F2200/294 ,  H03F2200/357 ,  H03F2200/451 ,  H03F2203/45246 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03G1/0029

Abstract: A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.

Abstract translation: 差分低噪声放大器（LNA）可在两种模式中的一种选择中操作。 LNA包括第一晶体管，第二晶体管，第三晶体管和第四晶体管。 在第一模式（PDC模式）中，四个晶体管被配置为作为后失真消除（PDC）LNA而工作。 第三和第四晶体管作为提高线性度的消除晶体管工作，但有一些降低LNA增益。 在第二模式（高增益模式）中，第三和第四晶体管被配置为使得它们输出的LNA输入信号的放大版本被加到由第一和第二主晶体管输出的LNA输入信号的放大版本， 增加收益。 在LNA中提供多路复用电路，使得LNA可以通过控制提供给LNA的数字模式控制信号来配置成两种模式中的可选择的一种。

公开(公告)号：US07405619B2

公开(公告)日：2008-07-29

申请号：US11467308

申请日：2006-08-25

Applicant: Tae Wook Kim

Inventor： Tae Wook Kim

IPC: H03F1/00

CPC classification number: H03F1/3205 ,  H03F1/0205 ,  H03F2200/357 ,  H03F2200/537 ,  H03F2203/45358

Abstract: Provided is a frequency converter using an amplification circuit that is improved with linearity by coupling a main transistor and an auxiliary transistor in parallel. An amplification circuit that is improved with linearity comprises an input block amplifying an input signal, an induction block inducing a current proportionate to an output signal of the input block and an amplification block comprising. The amplification block comprises a main transistor amplifying the output signal of the induction block, wherein the main transistor is biased to operate at a saturation region and an auxiliary transistor amplifying the output signal of the induction block, wherein the auxiliary transistor is biased to operate at a subthreshold region and coupled to the main transistor in parallel.

Abstract translation: 提供了一种使用通过并联耦合主晶体管和辅助晶体管而线性提高的放大电路的变频器。 以线性方式改进的放大电路包括放大输入信号的输入块，感应与输入块的输出信号成比例的电流的感应块和包括的放大块。 放大块包括放大感应块的输出信号的主晶体管，其中主晶体管被偏置以在饱和区域工作，而辅助晶体管放大感应块的输出信号，其中辅助晶体管被偏置以在 亚阈值区域并且并联耦合到主晶体管。

公开(公告)号：US20050248371A1

公开(公告)日：2005-11-10

申请号：US11083260

申请日：2005-03-16

Applicant: Hack-Soo Oh

Inventor： Hack-Soo Oh

IPC: H03F1/30 ,  H02M11/00 ,  H03F3/345

CPC classification number: H03F3/345 ,  H03F2200/357 ,  H03F2200/462

Abstract: A current to voltage amplifier in accordance with the present invention includes a current to voltage amplifier for receiving a sensor input to thereby output an amplified voltage corresponding to the sensor input including a bias current provider for providing a bias current, an input block for flowing a sensor current based on the sensor input, a first diode-connected MOS transistor for receiving the bias current from the bias current provider and providing the sensor current to the input block, and a first MOS transistor for flowing a remnant current subtracting the sensor current from the bias current, wherein the amplified voltage is corresponded to the current.

Abstract translation: 根据本发明的电流到电压放大器包括电流到电压放大器，用于接收传感器输入，从而输出对应于包括用于提供偏置电流的偏置电流提供器的传感器输入的放大电压，用于使 基于传感器输入的传感器电流，用于从偏置电流提供器接收偏置电流并向输入块提供传感器电流的第一二极管连接的MOS晶体管，以及用于将剩余电流从残留电流中减去传感器电流的第一MOS晶体管 偏置电流，其中放大的电压对应于电流。

公开(公告)号：US20150280658A1

公开(公告)日：2015-10-01

申请号：US14723044

申请日：2015-05-27

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: H03F3/00

CPC classification number: H03F3/16 ,  G11C27/024 ,  H03F3/005 ,  H03F3/62 ,  H03F3/70 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/357 ,  H03F2200/42 ,  H03H19/004 ,  H03M1/1245 ,  H03M1/468

Abstract: Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification.

Abstract translation: 具有电压增益基本上等于1的缓冲放大器实现的放大器电路。 在一个示例中，通过在缓冲放大器的输入端和输出端上施加输入源来实现连续时间放大器。 在另一示例中，实现了离散时间放大器。 在采样阶段期间，对至少一个输入电压进行采样，并且在传输阶段期间，至少一个电容器跨越缓冲放大器的输入端和输出端耦合以实现放大。

公开(公告)号：US07936214B2

公开(公告)日：2011-05-03

申请号：US12143623

申请日：2008-06-20

Applicant: Viacheslav Igorevich Suetinov

Inventor： Viacheslav Igorevich Suetinov

IPC: H03F1/26

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F3/211 ,  H03F2200/357 ,  H03F2200/513 ,  H03F2203/45246

Abstract: An apparatus and method for the cancellation of third order derivative distortion for ultra low power (ULP) applications are disclosed involving a first amplifier connected in parallel with a second amplifier for amplifying a received signal. The first amplifier includes at least one transistor operating in the sub-threshold region such that the first amplifier possesses a positive third derivative of a transfer function of the first amplifier, which generates a first amplified signal having in phase third order distortions. The second amplifier includes at least one differential pair of transistors operating in the sub-threshold region such that the second amplifier possesses a negative third derivative of a transfer function of the second amplifier, which generates a second amplified signal having in opposite phase third order distortions. The first and second amplified output signals are combined resulting in cancellation of third order distortions in the combined amplified signal.

Abstract translation: 公开了一种用于消除用于超低功率（ULP）应用的三阶微分失真的装置和方法，其涉及与用于放大接收信号的第二放大器并联连接的第一放大器。 第一放大器包括在子阈值区域中操作的至少一个晶体管，使得第一放大器具有第一放大器的传递函数的正三阶导数，其产生具有相位三阶失真的第一放大信号。 第二放大器包括在子阈值区域中操作的至少一个差动对晶体管，使得第二放大器具有第二放大器的传递函数的负三阶导数，其产生具有相反相位三阶失真的第二放大信号 。 第一和第二放大的输出信号被组合，导致组合的放大信号中的三阶失真的消除。

公开(公告)号：US20100308919A1

公开(公告)日：2010-12-09

申请号：US12799910

申请日：2010-05-03

Applicant: Jaroslaw Adamski ,  Daniel Losser ,  Vikas Sharma

Inventor： Jaroslaw Adamski ,  Daniel Losser ,  Vikas Sharma

IPC: H03F1/34 ,  H03K3/01 ,  H03F3/04

CPC classification number: H03F1/0261 ,  G05F1/56 ,  H03F1/0244 ,  H03F2200/357 ,  H03F2200/507

Abstract: Methods and devices for leakage current reduction are described. A regulator transistor is connected to a switch to bias the transistor with a first voltage during an ON state and a second voltage during the OFF state of the transistor. The switchable bias allows leakage current decrease and “on” resistance increase of the transistor.

Abstract translation: 描述了泄漏电流减少的方法和装置。 调节晶体管连接到开关以在导通状态期间以第一电压偏置晶体管，并在晶体管的截止状态期间施加第二电压。 可切换的偏置允许漏电流减小和晶体管的“导通”电阻增加。

公开(公告)号：US07750837B2

公开(公告)日：2010-07-06

申请号：US12185046

申请日：2008-08-01

Applicant: Chuanyang Wang ,  Xiaohong Quan ,  Seyfollah Bazarjani

Inventor： Chuanyang Wang ,  Xiaohong Quan ,  Seyfollah Bazarjani

IPC: H03M1/12

CPC classification number: H03F1/303 ,  H03F3/005 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/357 ,  H03F2200/447 ,  H03F2200/451 ,  H03M3/354 ,  H03M3/392 ,  H03M3/43 ,  H03M3/454

Abstract: Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ΣΔ ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.

Abstract translation: 描述用于自适应地产生开关电容器电路的偏置电流的技术。 开关电容电路以一个采样率对至少一个开关电容器进行充电和放电，并且可以是＆amp; ADC以采样率数字化模拟信号，并提供数字采样。 开关电容器电路可以支持与不同采样率相关联的多种模式。 偏置电路产生用于开关电容器电路的偏置电流与所选模式的采样率成比例，以提供与开关电容器电路内的工作跨导放大器（OTA）的采样率成比例的带宽，以及 以跟踪由于集成电路（IC）工艺和温度的变化而导致的开关电容器的变化。 开关电容器电路的稳定时间可以跟踪多种模式，并跨过IC工艺和温度变化。

公开(公告)号：US20090195310A1

公开(公告)日：2009-08-06

申请号：US12027107

申请日：2008-02-06

Applicant: Christian Holenstein ,  Junxiong Deng ,  Namsoo Kim

Inventor： Christian Holenstein ,  Junxiong Deng ,  Namsoo Kim

IPC: H03F3/45

CPC classification number: H03F3/193 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45188 ,  H03F2200/294 ,  H03F2200/357 ,  H03F2200/451 ,  H03F2203/45246 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03G1/0029

Abstract: A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.

Abstract translation: 差分低噪声放大器（LNA）可在两种模式中的一种选择中操作。 LNA包括第一晶体管，第二晶体管，第三晶体管和第四晶体管。 在第一模式（PDC模式）中，四个晶体管被配置为作为后失真消除（PDC）LNA而工作。 第三和第四晶体管作为提高线性度的消除晶体管工作，但有一些降低LNA增益。 在第二模式（高增益模式）中，第三和第四晶体管被配置为使得它们输出的LNA输入信号的放大版本被加到由第一和第二主晶体管输出的LNA输入信号的放大版本， 增加收益。 在LNA中提供多路复用电路，使得LNA可以通过控制提供给LNA的数字模式控制信号来配置成两种模式中的可选择的一种。