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公开(公告)号：US20090080581A1
公开(公告)日：2009-03-26
申请号：US12236342
申请日：2008-09-23
申请人： Axel Schuur , Ann P. Shen , Ali Tabatabaei
发明人： Axel Schuur , Ann P. Shen , Ali Tabatabaei
IPC分类号： H04B1/10
CPC分类号： H03H17/045 , H03H17/0292 , H03H2218/085
摘要： At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.
摘要翻译： 滤波器或其他数字处理的算术运算的至少一些可以顺序执行，这可以允许用于滤波器或其他数字处理的算术元件多次用于多个操作。
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公开(公告)号：US20090085789A1
公开(公告)日：2009-04-02
申请号：US12187632
申请日：2008-08-07
申请人： Axel Schuur , David H. Shen , Ann P. Shen
发明人： Axel Schuur , David H. Shen , Ann P. Shen
摘要： An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.
摘要翻译： 诸如CT SD-ADC的ADC包括产生充电和放电时钟信号的时钟产生电路，使得ADC中积分器的稳定时间增加。 时钟信号可以控制CT SD-ADC中的反馈SD-DAC。 时钟信号也可以是不对称的和/或可以导致积分器的建立时间大于系统时钟的一半。
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公开(公告)号：US20090088110A1
公开(公告)日：2009-04-02
申请号：US12236888
申请日：2008-09-24
申请人： Axel Schuur , Nianwei Xing , David H. Shen , Chien-Meen Hwang , Ann P. Shen , Niranjan Talwalkar
发明人： Axel Schuur , Nianwei Xing , David H. Shen , Chien-Meen Hwang , Ann P. Shen , Niranjan Talwalkar
IPC分类号： H04B1/16
摘要： A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.
摘要翻译： 射频接收机包括被配置为接收RF信号的无源混频器和被配置为接收无源混频器的输出的低输入阻抗电路。
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公开(公告)号：US07639088B2
公开(公告)日：2009-12-29
申请号：US12110048
申请日：2008-04-25
申请人： David H. Shen , Ann P. Shen , Axel Schuur
发明人： David H. Shen , Ann P. Shen , Axel Schuur
摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。
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公开(公告)号：US20090085622A1
公开(公告)日：2009-04-02
申请号：US12110048
申请日：2008-04-25
申请人： David H. Shen , Ann P. Shen , Axel Schuur
发明人： David H. Shen , Ann P. Shen , Axel Schuur
IPC分类号： H03L7/06
摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。
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公开(公告)号：US20100329157A1
公开(公告)日：2010-12-30
申请号：US12495064
申请日：2009-06-30
申请人： Nianwei Xing , David H. Shen , Axel Schuur , Ann P. Shen
发明人： Nianwei Xing , David H. Shen , Axel Schuur , Ann P. Shen
CPC分类号： H03F3/45183 , H03F1/3211 , H03F2203/45342
摘要： Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.
摘要翻译： 用于差分电路的电路和方法涉及具有多对具有背栅极端子的差分晶体管中的一个，其中每个背栅极端子被可调谐的栅极电压偏置以补偿差分电路中的电路不匹配并且减小 或消除输出信号中的偶次谐波。 补偿电路可以被配置为接收与差分电路的差分输出信号相关的数据，并且向差分晶体管的背栅极端子提供一个或多个反向栅极电压，以调整差分晶体管的阈值电压并抑制 差分电路的差分输出信号中的偶次谐波。
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公开(公告)号：US07646325B2
公开(公告)日：2010-01-12
申请号：US12187632
申请日：2008-08-07
申请人： Axel Schuur , David H. Shen , Ann P. Shen
发明人： Axel Schuur , David H. Shen , Ann P. Shen
IPC分类号： H03M1/12
摘要： An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.
摘要翻译： 诸如CT SD-ADC的ADC包括产生充电和放电时钟信号的时钟产生电路，使得ADC中积分器的稳定时间增加。 时钟信号可以控制CT SD-ADC中的反馈SD-DAC。 时钟信号也可以是不对称的和/或可以导致积分器的建立时间大于系统时钟的一半。
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公开(公告)号：US20090088124A1
公开(公告)日：2009-04-02
申请号：US12237038
申请日：2008-09-24
申请人： Axel Schuur , Ann P. Shen
发明人： Axel Schuur , Ann P. Shen
IPC分类号： H04B1/16
CPC分类号： H04B1/006
摘要： A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal. A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal. An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms. Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard.
摘要翻译： 接收机包括配置成接收RF输入信号并产生放大的RF信号的共栅低噪声放大器（LNA）。 下变频无源混频器被配置为将放大的接收RF输入信号与由本地振荡器产生的本地振荡器信号混合以产生下变频放大信号。 放大器被配置为放大下变频信号并具有欧姆量级的输入阻抗。 在多频段通信标准的所有频段，只需要一个LNA来接收RF输入。
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公开(公告)号：US20090079497A1
公开(公告)日：2009-03-26
申请号：US12114344
申请日：2008-05-02
申请人： Axel Schuur , Ann Shen
发明人： Axel Schuur , Ann Shen
摘要： A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.
摘要翻译： 差分分频器包括每个被配置为接收差分输入信号的第一和第二输入端。 分频器还包括被配置为产生第一输出信号的第一输出端和被配置为产生第二输出信号的第二输出端。 分压器还包括耦合到第一输出端的第三输入端和耦合到第二输出端的第四输入端。 此外，分频器包括第一可变电流源。 改变第一可变电流源的电流导致第一输出端的第一输出信号和第二输出端的第二输出信号之间的相位差的改变。
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