公开(公告)号：US4935646A

公开(公告)日：1990-06-19

申请号：US314525

申请日：1989-02-22

Applicant: Charles W. Peterson, Jr. ,  Steven J. Quinlan

Inventor： Charles W. Peterson, Jr. ,  Steven J. Quinlan

IPC: H03K19/0948 ,  G11C8/10 ,  H03K19/173 ,  H03M7/00

CPC classification number: G11C8/10 ,  H03K19/1738 ,  H03M7/005

Abstract: A static, single-ended cascode voltage switch logic system arranged in a tree with multiple levels. Each level of each branch of the tree is comprised of a complementary pair. The invention is preferrably implemented in CMOS, so that each complementary pair consists of a p-type and an n-type transistor, the p-type FET connected at its source to a high voltage reference and at its drain to the drain of the n-type FET. The source of the n-type FET is connected to the common drain connections of the next lower-level complementary pair, or to a low voltage reference. The approach eliminates the need for passive loads, clocked loads or complementary signals, since each node is actively held high or low.

公开(公告)号：US4491839A

公开(公告)日：1985-01-01

申请号：US373818

申请日：1982-04-30

Applicant: Fritz G. Adam

Inventor： Fritz G. Adam

IPC: H03M7/22 ,  H03K17/693 ,  H03M7/00 ,  H04Q9/00

CPC classification number: H03K17/693 ,  H03M7/005

Abstract: In a circuit for selecting a random number (N) of potentials (Ui . . . ), which is integrated in accordance with the complementary insulated-gate field-effect transistor technique, one transmission gate (G . . . ) is associated with each potential, with the switching section of the gate lying between the potential (Ui . . . ) and the output (U), and the two control inputs of the respective transmission gate (G . . . ) are connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder. This decoder may consist of a 1-ex-n-open-circuit-decoder (SD) and of a 1-ex-n-short-circuit decoder (KD) whose address inputs are connected in pairs to one another and whose like outputs (1 . . . 8) are connected to one another. The open-circuit decoder (SD) consists of transistors (TP) of the one channel conductivity type, and the short-circuit decoder (KD) consists of transistors (TN) of the other channel conductivity type.

Abstract translation: 在用于选择根据互补绝缘栅场效应晶体管技术集成的随机数（N）电位（Ui ...）的电路中，一个传输门（...）与每个 电位，门的开关部分位于电位（U i ...）和输出（U）之间，并且相应传输门（...）的两个控制输入直接或分别连接 相关的逆变器（I ...）到CMOS-1-ex-n解码器的相应输出。 该解码器可以由1-n开路解码器（SD）和1-ex-n-short-circuit解码器（KD）组成，其地址输入彼此成对连接并且具有类似的输出 （1 ... 8）彼此连接。 开路解码器（SD）由一个沟道导电类型的晶体管（TP）组成，短路解码器（KD）由另一个沟道导电类型的晶体管（TN）组成。

公开(公告)号：US4165504A

公开(公告)日：1979-08-21

申请号：US895849

申请日：1978-04-13

Applicant: James J. Remedi

Inventor： James J. Remedi

IPC: H03M7/00 ,  H04Q3/00

CPC classification number: H03M7/005

Abstract: A CMOS digital decoder has a plurality of circuits having first and second output nodes. A first transistor is used to precharge the first output node and a second transistor is used to precharge the second output node. A third transistor responsive to an enable signal is used to enable the decoder. A fourth transistor is coupled between the third transistor and the first output node and a fifth transistor is coupled between the third transistor and the second output node. A plurality of transistors can be in series between the fourth transistor and the third transistor, or the plurality of transistors can be in parallel between the first and second output nodes depending upon the type of decoder output desired. The decoder can be made a static decoder by coupling a pair of back-to-back inverters to each of the output nodes.

Abstract translation: CMOS数字解码器具有多个具有第一和第二输出节点的电路。 第一晶体管用于对第一输出节点进行预充电，第二晶体管用于对第二输出节点进行预充电。 响应于使能信号的第三晶体管用于使能解码器。 第四晶体管耦合在第三晶体管和第一输出节点之间，第五晶体管耦合在第三晶体管和第二输出节点之间。 多个晶体管可以串联在第四晶体管和第三晶体管之间，或者多个晶体管可以在第一和第二输出节点之间并联，这取决于所需的解码器输出的类型。 通过将一对背对背反相器耦合到每个输出节点，可以将解码器制成静态解码器。

公开(公告)号：US11962335B2

公开(公告)日：2024-04-16

申请号：US18144524

申请日：2023-05-08

Applicant: Google LLC

Inventor： Reiner Alwyn Pope

IPC: H03M7/00 ,  H03M7/30 ,  H03M7/42

CPC classification number: H03M7/42 ,  H03M7/005 ,  H03M7/6011

Abstract: Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

公开(公告)号：US5166554A

公开(公告)日：1992-11-24

申请号：US592354

申请日：1990-10-02

Applicant: Chitranjan N. Reddy ,  Roger D. Norwood

Inventor： Chitranjan N. Reddy ,  Roger D. Norwood

IPC: G11C8/10 ,  H03K19/017 ,  H03M7/00

CPC classification number: G11C8/10 ,  H03K19/01714 ,  H03M7/005

Abstract: A boot-strapped decoder circuit in accordance with the present invention activates a selected word line output in response to an input address. The decoder circuit includes a plurality of row decoders, each of which has a plurality of word line outputs. The row decoders respond to a select signal that identifies one of the row decoders as a selected row decoder. The select signal is generated by a regular predecoder based on the most significant bits of the input address. Low order predecoder circuitry utilizes the least significant bits of the input address to generate a low order decoder signal. The selected row decoder includes boosting means coupled to each of the selected row decoder outputs and responsive to the low order predecode signal for generating a boot-strapped output voltage on a selected word line output of the selected row decoder.

Abstract translation: 根据本发明的引导带解码器电路响应于输入地址激活所选择的字线输出。 解码器电路包括多个行解码器，每个行解码器具有多个字线输出。 行解码器响应于将行解码器中的一个识别为所选行解码器的选择信号。 选择信号由基于输入地址的最高有效位的常规预解码器生成。 低阶预解码器电路利用输入地址的最低有效位来产生低阶解码器信号。 选择的行解码器包括耦合到所选择的行解码器输出中的每一个并且响应于低阶预解码信号的升压装置，用于在所选行解码器的选定字线输出上产生引导带输出电压。

公开(公告)号：US4438427A

公开(公告)日：1984-03-20

申请号：US926950

申请日：1978-07-20

Applicant: Kenichi Miura

Inventor： Kenichi Miura

IPC: G06F5/00 ,  G06F9/30 ,  H01L27/02 ,  H03K19/177 ,  H03M7/00 ,  H03K13/24

CPC classification number: H03K19/17708 ,  H01L27/0207 ,  H03M7/005

Abstract: Decoder and method utilizing logic circuitry for decoding multi-bit digital signals. An input decoder decodes subsets of the input signals to provide a plurality of intermediate signals which are selectively combined to provide output signals which represent a desired decoding of the input signals. The intermediate signals are applied to generally parallel bus lines which extend centrally of the substrate on which the decoder is constructed. The logic circuits are arranged in blocks along both sides of the bus lines, with all of the bus lines extending past all of the logic blocks, and conductors extending transversely of the bus lines carry the appropriate intermediate signals from the bus lines to the logic blocks.

Abstract translation: 解码器和方法利用逻辑电路解码多位数字信号。 输入解码器解码输入信号的子集以提供多个中间信号，其被选择性地组合以提供表示输入信号的期望解码的输出信号。 中间信号被施加到大致平行的总线，其延伸在构成解码器的衬底的中心。 逻辑电路沿着总线的两侧排列成块，所有总线延伸通过所有逻辑块，并且横向于总线延伸的导线承载从总线到逻辑块的适当的中间信号 。

公开(公告)号：US4275312A

公开(公告)日：1981-06-23

申请号：US964894

申请日：1978-11-30

Applicant: Tsuyoshi Saitou ,  Tsuneo Ito

Inventor： Tsuyoshi Saitou ,  Tsuneo Ito

IPC: G11C11/41 ,  G11C11/413 ,  G11C11/418 ,  H03M7/00 ,  H03K19/094 ,  G11C8/00 ,  H03K19/20

CPC classification number: G11C11/418 ,  H03M7/005

Abstract: The present invention relates to a transistor circuit, and more specifically to a static decoder circuit made up of a series circuit of a NOR logic gate circuit consisting of a plurality of MISFET's for receiving address signals through the gates, an inverter circuit for receiving the output of the logic gate circuit through the gate, a first MISFET for receiving the output of the logic gate circuit through the gate, and a second MISFET for receiving the output of the inverter circuit through the gate, wherein said NOR logic gate circuit and inverter circuit are connected to a ground terminal via a first switching MISFET which receives the control signals through the gate, and said series circuit is connected to a power supply terminal via a second switching MISFET which receives the control signals through the gate. According to the circuit of the present invention, said first and second switching MISFET's are rendered off by said control signals during the standby periods, such that the current pass is completely interrupted between the power supply terminal and the ground terminal in the decoder circuit, and the output of the decoder circuit is rendered to acquire the ground level.

Abstract translation: 晶体管电路技术领域本发明涉及一种晶体管电路，更具体地涉及一种由逻辑门电路的串联电路构成的静态解码电路，该逻辑门电路由多个用于通过栅极接收地址信号的MISFET构成，反相器电路用于接收输出 通过栅极的逻辑门电路的第一MISFET，用于通过栅极接收逻辑门电路的输出的第一MISFET和用于通过栅极接收反相器电路的输出的第二MISFET，其中所述NOR逻辑门电路和反相器电路 经由通过栅极接收控制信号的第一开关MISFET连接到接地端子，并且所述串联电路经由通过栅极接收控制信号的第二开关MISFET连接到电源端子。 根据本发明的电路，在待机期间，通过所述控制信号使所述第一和第二开关MISFET被截止，使得解码器电路中的电源端子和接地端子之间的电流通过完全中断，以及 使解码器电路的输出获得地电平。

公开(公告)号：US11831341B2

公开(公告)日：2023-11-28

申请号：US17001580

申请日：2020-08-24

Applicant: Arm Limited

Inventor： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: H03M7/00 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/21 ,  H03M7/30

CPC classification number: H03M7/005 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/215 ,  H03M7/6011

Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

公开(公告)号：US11728826B2

公开(公告)日：2023-08-15

申请号：US17328452

申请日：2021-05-24

Applicant: Google LLC

Inventor： Reiner Alwyn Pope

IPC: H03M7/00 ,  H03M7/42 ,  H03M7/30

CPC classification number: H03M7/42 ,  H03M7/005 ,  H03M7/6011

Abstract: Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

公开(公告)号：US20120110418A1

公开(公告)日：2012-05-03

申请号：US13059808

申请日：2010-10-29

Applicant: Xudong Ma

Inventor： Xudong Ma

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1157 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  H03M7/005 ,  H03M13/1171

Abstract: Technologies are generally described herein for encoding a message. Technologies are also generally described herein for decoding an encoded message. The message may be encoded and/or decoded according to a mapping rule. The mapping rule may enable multiple messages to be successively written to the same block in a solid state drive without an erasure operation.

Abstract translation: 本文一般地描述了用于编码消息的技术。 本文一般还描述了用于解码编码消息的技术。 消息可以根据映射规则进行编码和/或解码。 映射规则可以使得多个消息能够被连续地写入固态驱动器中的同一块而不进行擦除操作。