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1.发明申请公开(公告)号：US20190068220A1
公开(公告)日：2019-02-28
申请号：US16010026
申请日：2018-06-15
发明人： Naveen KUMAR , Aman BHATIA , Chenrong XIONG , Yu CAI , Fan ZHANG
摘要： A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder that may be included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.
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公开(公告)号：US20180276161A1
公开(公告)日：2018-09-27
申请号：US15909702
申请日：2018-03-01
发明人： Sungjoon AHN
IPC分类号： G06F13/40 , G06F11/22 , G06F9/4401
CPC分类号： G06F13/4009 , G06F9/4411 , G06F11/2221 , G06F13/404 , G06F13/4221
摘要： A memory system and an operating method thereof include: at least a host; and at least PCIe coupled with the host, wherein the at least PCIe link includes at least a PCIe switch and a plurality of PCIe endpoints, wherein the plurality of PCIe endpoints includes used PCIe endpoints and unused PCIe endpoints, the used PCIe endpoints are mapped into a PCIe enumeration tree, and the unused PCIe endpoints are removed from the PCIe enumeration tree, at virtual switch mode.
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公开(公告)号：US20180137003A1
公开(公告)日：2018-05-17
申请号：US15353389
申请日：2016-11-16
发明人： David J. Pignatelli , Fan Zhang , Yu Cai
CPC分类号： G06F11/1012
摘要： A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.
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公开(公告)号：US09906241B2
公开(公告)日：2018-02-27
申请号：US14948197
申请日：2015-11-20
发明人： Naveen Kumar , Aman Bhatia , Lingqi Zeng
CPC分类号： H03M13/2963 , H03M13/098 , H03M13/152 , H03M13/29 , H03M13/2909 , H03M13/2921 , H03M13/2936 , H03M13/2966
摘要： An apparatus for a turbo product codes includes a codeword generator and an interleaver. The codeword generator receives a data in a matrix, and generate a turbo product code (TPC) codeword including the data, row parities and column parities. The interleaver interleaves the TPC codeword by assigning at least one bit in at least one row-column intersection of the TPC codeword to at least one master code, and outputs the interleaved TPC codeword.
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公开(公告)号：US20180047444A1
公开(公告)日：2018-02-15
申请号：US15663527
申请日：2017-07-28
发明人： David PIGNATELLI , Fan ZHANG
CPC分类号： G11C11/5642 , G06F3/0614 , G06F3/0647 , G06F3/0653 , G06F3/0679 , G11C16/0458 , G11C16/0483 , G11C16/26 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric OVS read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric OVS read with at least the initial read threshold, and create an asymmetric read result; adjust the initial read threshold according to at least the symmetric read result and asymmetric read result, and create an optimal read threshold; and execute data recovery process with the optimal read threshold.
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公开(公告)号：US09842023B2
公开(公告)日：2017-12-12
申请号：US15007996
申请日：2016-01-27
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/1072 , G11C16/26 , G11C16/34 , G11C16/3431 , G11C16/349 , G11C29/52 , H03M13/1102
摘要： A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value.
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公开(公告)号：US09823863B1
公开(公告)日：2017-11-21
申请号：US14714017
申请日：2015-05-15
发明人： Hong Lu , Nahir Sarmicanic , Suneel Kumar Indupuru
CPC分类号： G06F3/0619 , G06F3/0613 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0683 , G06F3/0688 , G06F12/0292 , G06F2212/1016
摘要： Data associated with logical addresses are received where the data is to be stored on a plurality of solid state storage dies and each of the plurality of solid state storage dies is independently accessible. Metadata is generated that includes the logical addresses where the metadata and the data sum to an amount of information that is less than a maximum amount of information that can be written to the plurality of solid state storage dies in a single write operation. The metadata and the data are stored in the plurality of solid state storage dies.
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公开(公告)号：US20170330607A1
公开(公告)日：2017-11-16
申请号：US15595664
申请日：2017-05-15
发明人： Yungcheng LO
CPC分类号： G11C8/12 , G06F11/1012 , G06F11/141 , G06F11/1666 , G06F11/30 , G11C16/04 , G11C16/26 , G11C16/34 , G11C16/349 , G11C29/00 , G11C29/028 , G11C29/42 , G11C29/50004 , G11C29/52 , G11C2211/563
摘要： A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ECC engine.
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公开(公告)号：US20170310316A1
公开(公告)日：2017-10-26
申请号：US15482553
申请日：2017-04-07
发明人： Chun-Ju SHEN , Jenn-Gang CHERN
CPC分类号： H03K7/08 , H03K5/135 , H03K5/1565 , H03K2005/00052 , H03K2005/00058
摘要： The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.
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公开(公告)号：US20170285945A1
公开(公告)日：2017-10-05
申请号：US15476503
申请日：2017-03-31
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G06F2212/7205
摘要： A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (GC)/HOST ratio based on at least a part of invalid count of garbage collection (GC) blocks and valid count of BGC blocks, and adjust throttling parameters of commands in accordance with the GC/HOST ratio and a number of erased blocks.
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