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公开(公告)号：US07120769B2
公开(公告)日：2006-10-10
申请号：US10796454
申请日：2004-03-08
申请人： Yuichi Yagawa , Naoki Watanabe , Shigeru Kishiro
发明人： Yuichi Yagawa , Naoki Watanabe , Shigeru Kishiro
IPC分类号： G05F12/00
CPC分类号： G06F11/2064 , G06F11/2058 , Y10S707/99953 , Y10S707/99955
摘要： A method for copying data to multiple remote sites includes transmitting data from a first volume in a primary storage system to a back-up volume provided in a secondary storage system. The primary storage system is located at a primary site, and the secondary storage system is located at a first remote site from the primary site. The data from the first volume in the primary storage system is copied to a second volume in the primary storage system using a point in time (PiT) as a reference point of time for the copying. The second volume is provided with a first time consistent image of the first volume with respect to the reference point of time. The data from the second volume in the primary storage system is transferred to a third volume in a ternary storage system at a second remote site. The third volume is provided with a second time consistent image of the second volume with respect to the reference point of time, where the second time consistent image is a mirror image of the first time consistent image. The data from the third volume is transferred to a fourth volume in the ternary storage system. The fourth volume is provided with a third time consistent image. In the ternary storage, either of the third volume or fourth volume can always keep time consistent image of the first volume.
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2.发明授权Virtual multi-port RAM employing multiple accesses during single machine cycle 失效虚拟多端口RAM在单机周期中采用多次访问
公开(公告)号：US5542067A
公开(公告)日：1996-07-30
申请号：US345328
申请日：1994-11-21
CPC分类号： G11C8/16 , G11C7/103 , G11C7/1072
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译： 虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。 定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。 每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。 多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。 类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。
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公开(公告)号：US07685167B2
公开(公告)日：2010-03-23
申请号：US11669005
申请日：2007-01-30
申请人： Doug Mueller
发明人： Doug Mueller
IPC分类号： G05F12/00
CPC分类号： G06Q10/06
摘要： A reference instance for use in a configuration management system is a configuration item that may be associated with a number of assets, all of which share a common set of attributes. The use of reference instances permits a single configuration item to identify a potentially large number of assets. This may be particularly useful for identifying and tracking low-priority assets where the detail or amount of information needed to effectively track and manage the asset is relatively small. Use of reference instance configuration items allows an organization to identify and manage virtually all of their assets without the cost and effort of creating large numbers of substantially identical configuration items.
摘要翻译： 在配置管理系统中使用的参考实例是可以与多个资产相关联的配置项，所有这些资产都共享一组共同的属性。 使用引用实例允许单个配置项来识别潜在的大量资产。 这对于识别和跟踪低优先级资产特别有用，其中有效跟踪和管理资产所需的详细信息量或信息量相对较小。 使用参考实例配置项允许组织识别和管理几乎所有的资产，而无需创建大量基本相同的配置项的成本和努力。
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公开(公告)号：US06865654B2
公开(公告)日：2005-03-08
申请号：US10206952
申请日：2002-07-30
申请人： Joo-seon Kim
发明人： Joo-seon Kim
CPC分类号： G06F5/14 , G06F5/06 , G06F5/065 , G06F13/385 , G06F2205/067
摘要： A device for interfacing asynchronous data, and more particularly, a device for interfacing asynchronous data using a first-in-first-out (FIFO) for preventing cutoff in data transfer by transferring the asynchronous data in accordance with a data transfer information signal while best satisfying a transfer request from a host between two devices that transfer the bi-directional asynchronous data. The provided device prevents control problems caused by the asynchronous data, so that the selected data is precisely and stably transferred even if the transfer speed is increased to equal that of an inner system clock. In addition, the output speed of a flag signal is faster than that of an existing method in which read and write addresses are compared, so that the remaining amount of data in the FIFO is precisely measured. As a result, asynchronous data is stably interfaced at a high speed.
摘要翻译： 一种用于接口异步数据的装置，更具体地说，一种用于使用先进先出（FIFO）对接异步数据的装置，用于通过根据数据传输信息信号传送异步数据同时最佳地防止数据传输中的切断 满足传输双向异步数据的两个设备之间的主机的传输请求。 所提供的设备防止由异步数据引起的控制问题，使得即使传输速度增加到内部系统时钟的传输速度也能精确且稳定地传送所选择的数据。 此外，标志信号的输出速度比其中比较读取和写入地址的现有方法的输出速度更快，从而精确地测量FIFO中的剩余数据量。 结果，异步数据以高速稳定地接口。
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5.发明授权Method and system for decreasing power consumption in memory arrays having usage-driven power management 失效具有使用驱动电源管理的存储器阵列中的功率消耗降低的方法和系统公开(公告)号：US08010764B2
公开(公告)日：2011-08-30
申请号：US11176819
申请日：2005-07-07
IPC分类号： G05F12/00
CPC分类号： G06F1/3275 , G06F1/3225 , G11C5/14 , Y02D10/13 , Y02D10/14
摘要： A method and system for decreasing power consumption in memory arrays having usage-driven power management provides decreased power consumption in the memory array of a processing system. Per-page usage information is gathered on memory by a memory controller and periodically evaluated by software. The software distinguishes between more frequently accessed pages and less frequently accessed pages by analyzing the gathered usage information and periodically migrates physical memory pages in order to group less frequently accessed pages and more frequently access pages in separately power-managed memory ranks. When used in conjunction with a usage-driven power management mechanism, the ranks containing the less frequently accessed pages can enter deeper power-saving states and/or any power-saving state for longer periods. Operation may be further enhanced by using packed allocation in the memory ranks containing the less-frequently accessed pages and scattered allocation in the memory ranks having more frequently accessed pages.
摘要翻译： 用于降低具有使用驱动功率管理的存储器阵列中的功率消耗的方法和系统提供了处理系统的存储器阵列中的功耗降低。 每页使用信息由存储器控制器收集在存储器上，并由软件定期评估。 该软件通过分析收集的使用信息来区分更频繁访问的页面和较不频繁访问的页面，并周期性地迁移物理内存页面，以便分组较不频繁访问的页面，并且更频繁地在单独的功率管理内存等级中访问页面。 当与使用驱动的电源管理机制结合使用时，包含较不频繁访问的页面的行列可以在更长的时间内进入更深的省电状态和/或任何省电状态。 可以通过在包含较不频繁访问的页面的内存列中使用打包分配以及具有更频繁访问的页面的内存级别中的分散分配来进一步增强操作。
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公开(公告)号：US07284110B2
公开(公告)日：2007-10-16
申请号：US11424388
申请日：2006-06-15
IPC分类号： G05F12/00
CPC分类号： G06F9/5016 , G06F9/5061
摘要： Method, apparatus and article of manufacture for determining memory requirements for a partition manager based on a given configuration. In one embodiment, a quantity of memory required for each of a plurality of components is determined, where each component is a collection of function-related code portions. Then, a total quantity of memory required for the partition manager based on the quantities of memory required for the plurality of components is determined.
摘要翻译： 基于给定配置来确定分区管理器的存储器需求的方法，装置和制造。 在一个实施例中，确定多个组件中的每一个所需的存储量，其中每个组件是与功能相关的代码部分的集合。 然后，确定基于多个部件所需的存储量的分区管理器所需的总存储量。
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公开(公告)号：US07136488B2
公开(公告)日：2006-11-14
申请号：US10059217
申请日：2002-01-31
CPC分类号： G06F9/30178 , G06F9/30003 , G06F9/3004 , G06F9/30156 , G06F12/0802 , G06F21/72
摘要： In a microprocessor that internally has a microprocessor specific secret key, a key management unit is provided to carry out a key registration for reading out from an external memory a distribution key that is obtained in advance by encrypting the instruction key by using a public key corresponding to the secret key, decrypting the distribution key by using the secret key to obtain the instruction key, and registering the instruction key in correspondence to a specific program identifier for identifying the program into a key table, and to notify a completion of the key registration to the processor core asynchronously by interruption when the key registration is completed.
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公开(公告)号：US06898668B2
公开(公告)日：2005-05-24
申请号：US10179727
申请日：2002-06-24
CPC分类号： G06F3/064 , G06F3/0605 , G06F3/0608 , G06F3/0689 , G06F11/1092 , G06F2211/1035 , G11B27/002 , G11B27/105 , G11B2220/2516 , G11B2220/415
摘要： A method of operating a storage controller that receives data access requests containing a logical block address and a count of blocks involved in the access request. A record is generated and persistently stored indicating whether particular logical block addresses have been accessed since creation. The persistent record is subsequently accessed to enable selected operations to be skipped or aborted when they selected operations involve logical block addresses that have never been accessed.
摘要翻译： 一种操作存储控制器的方法，该存储控制器接收包含逻辑块地址的数据访问请求和访问请求中涉及的块的计数。 生成并持续存储记录，指示自创建以来是否已经访问了特定的逻辑块地址。 随后访问持久性记录，以便当选择的操作涉及从未访问的逻辑块地址时，可以跳过或中止所选择的操作。
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