公开(公告)号：US06578253B1

公开(公告)日：2003-06-17

申请号：US08236378

申请日：1994-05-02

申请人： Edward Herbert

发明人： Edward Herbert

IPC分类号： H01E706

CPC分类号： H01F27/22 ,  H01F5/04 ,  H01F27/06 ,  H01F27/29 ,  H01F2038/006 ,  Y10T29/4902 ,  Y10T29/49071

摘要： A matrix transformer and/or inductor module has its terminations bonded rigidly to the ferrite core of which it is made. Because the ferrite core is strong and dimensionally stable, the terminations are rugged and precisely located, important criteria for assembly to printed circuit boards and the like, especially if automated assembly methods are used. In another embodiment, the module has top and bottom metal plates which are the high current output terminals. This module can be mounted sandwiched between live heat sinks. In another embodiment, deep grooves are made into the core material, and fins are bonded into the grooves. The grooves reduce core losses by reducing eddy currents and dimensional resonance effects, and the fins remove heat from within the core allowing operation at much higher flux density and frequency.

摘要翻译： 矩阵变压器和/或电感器模块具有刚性地结合到其所制造的铁氧体磁芯的端接件。 因为铁氧体磁芯是坚固的并且尺寸稳定的，所以端子是坚固的并且精确地定位，用于组装到印刷电路板等的重要标准，特别是如果使用自动组装方法。 在另一个实施例中，该模块具有作为高电流输出端子的顶部和底部金属板。 该模块可以夹在活的散热器之间。 在另一个实施例中，将深槽制成芯材，并将鳍结合到槽中。 凹槽通过减小涡流和尺寸共振效应来减小磁芯损耗，并且散热片从核心内消除热量，从而允许在更高的通量密度和频率下工作。

公开(公告)号：US06455329B1

公开(公告)日：2002-09-24

申请号：US10022512

申请日：2001-12-20

申请人： Nam Kyeong Kim ,  Seung Jin Yeom

发明人： Nam Kyeong Kim ,  Seung Jin Yeom

IPC分类号： H01E706

CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/02356 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/55

摘要： A method for fabricating a capacitor in a semiconductor device includes forming a semiconductor device having a source, a drain, and a gate on a semiconductor substrate, forming an interlayer insulating film having a contact hole exposing the source, forming a conductive layer in the contact hole, forming a lower electrode on the interlayer insulating film, inclusive of the conductive layer, coating an insulating material on the lower electrode for forming a dielectric film, subjecting the insulating material to a first rapid thermal annealing of a first temperature in a chamber, to form nuclei oriented along an a-b axis, subjecting the insulating material to a second rapid thermal annealing at a second temperature higher than the first temperature in the chamber, to grow the nuclei oriented along the a-b axis, to form a dielectric film, and forming an upper electrode on the dielectric film.

摘要翻译： 一种在半导体器件中制造电容器的方法包括在半导体衬底上形成具有源极，漏极和栅极的半导体器件，形成具有暴露源极的接触孔的层间绝缘膜，在接触中形成导电层 在层间绝缘膜上形成下电极，包括导电层，在用于形成电介质膜的下电极上涂覆绝缘材料，对绝缘材料进行室内第一温度的第一快速热退火， 以形成沿着ab轴取向的核，使绝缘材料在室内比第一温度高的第二温度进行第二快速热退火，以使沿着ab轴取向的核生长，形成电介质膜，并形成 电介质膜上的上电极。

公开(公告)号：US06238932B1

公开(公告)日：2001-05-29

申请号：US09231023

申请日：1999-01-14

申请人： Katsuhiro Aoki ,  Tomoyuki Sakoda ,  Yukio Fukuda

发明人： Katsuhiro Aoki ,  Tomoyuki Sakoda ,  Yukio Fukuda

IPC分类号： H01E706

CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

摘要： A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).

摘要翻译： 一种强电介质电容器电极接触结构，包括放置在衬底（2）上并且在衬底（2）和绝缘体（4）之间包含晶体管源（6）和晶体管漏极（8）的绝缘体（4）。 绝缘体（4）包含源极插头（10）和导电排放塞（12）。 晶体管源（6）电连接到源极（10）。 晶体管漏极（8）电连接到导电排放塞（12）。 晶体管栅极（14）位于源极插头（10）和导电排放塞（12）之间，并被绝缘体（4）容纳。 金属布线（16）电连接到源插头（10）。 隔离膜（18）放置在绝缘体（4）和导电排放塞（12）之上。 底部电极（20）放置在阻挡膜（18）上方。 铁电层（22）放置在底部电极（20）上。 顶部电极（24）被放置在铁电层（22）上方。