公开(公告)号：USRE37507E1

公开(公告)日：2002-01-15

申请号：US08820812

申请日：1997-03-28

申请人： Je-Chang Jung

发明人： Je-Chang Jung

IPC分类号： H03M746

CPC分类号： H03M7/42 ,  H03M7/48 ,  H04N19/115 ,  H04N19/124 ,  H04N19/13 ,  H04N19/132 ,  H04N19/146 ,  H04N19/149 ,  H04N19/176 ,  H04N19/192 ,  H04N19/196 ,  H04N19/197 ,  H04N19/60 ,  H04N19/61 ,  H04N19/91 ,  H04N19/93

摘要： A method of variable length coding/decoding of image data and an apparatus thereof can vary the length of an escape sequence during variable length coding to thereby reduce the amount of transmitted data. The method of variable length coding/decoding includes the steps of loading an initial potential maximum run length; determining a number of bits necessary to express the potential maximum run length, coding a run length using the necessary number of bits and decreasing the potential maximum ran length by an amount equal to the previously coded run length to arrive at a new potential maximum ran length until an end of a block to be encoded has been reached.

摘要翻译： 可变长度编码/解码图像数据的方法及其装置可以在可变长度编码期间改变转义序列的长度，从而减少发送数据量。可变长度编码/解码方法包括以下步骤： 初始潜在​​最大游程长度; 确定表达潜在最大游程长度所必需的位数，使用必要数量的比特编码游程长度，并将潜在最大游程长度减小等于先前编码的游程长度的量，以获得新的潜在最大游程长度 直到达到要编码的块的结尾。

公开(公告)号：US06384747B1

公开(公告)日：2002-05-07

申请号：US09694587

申请日：2000-10-23

申请人： David E. Reed ,  Jay N. Livingston ,  Marvin L. Vis

发明人： David E. Reed ,  Jay N. Livingston ,  Marvin L. Vis

IPC分类号： H03M746

CPC分类号： G06T9/005 ,  G11B20/1426 ,  H03M5/145 ,  H03M7/46 ,  H03M7/48

摘要： Data storage system circuitry comprises randomizer circuitry and run-length control circuitry. The randomizer circuitry generates randomized user data. The run-length control circuitry grades the randomized user data to determine if the randomized user data requires run-length encoding. The run-length control circuitry applies the run-length encoding to the randomized user data if the randomized user data requires run-length encoding. The run-length control circuitry may encode decoding information and error correction information for the decoding information into the randomized user data. The run-length encoding may comprise de-randomization or RLL encoding. If de-randomization is used, RLL encoding may be eliminated altogether for the randomized user data.

摘要翻译： 数据存储系统电路包括随机化电路和游程长度控制电路。 随机化电路产生随机用户数据。 游程长度控制电路对随机用户数据进行分级，以确定随机用户数据是否需要运行长度编码。 如果随机用户数据需要运行长度编码，则游程长度控制电路将游程长度编码应用于随机用户数据。 游程长度控制电路可以将用于解码信息的解码信息和纠错信息编码为随机用户数据。 游程长度编码可以包括去随机化或RLL编码。 如果使用去随机化，对于随机用户数据可以完全消除RLL编码。

公开(公告)号：US06333705B1

公开(公告)日：2001-12-25

申请号：US09545189

申请日：2000-04-07

申请人： Isabelle Amonou ,  Félix Henry

发明人： Isabelle Amonou ,  Félix Henry

IPC分类号： H03M746

CPC分类号： H04N19/645 ,  H04N19/10 ,  H04N19/102 ,  H04N19/115 ,  H04N19/146 ,  H04N19/147 ,  H04N19/63

摘要： In order to code a digital signal, it is decomposed (20) into several subsignals; each subsignal is coded (38) by means of a coding technique taken from amongst M coding techniques Ci; and the stream of coded bits thus produced is entered (40) in a first part of a file intended to receive the coded digital signal. Then the application, successively to each coded subsignal, of each decoding technique Di associated with the coding technique Ci is simulated (48); and if and only if at least two different decoding techniques are acceptable, within the meaning of a predetermined likelihood criterion, for decoding the same coded subsignal, there is entered (52) in a second part of the file information making it possible to select, during decoding, the decoding technique associated with the coding technique used for coding this subsignal.

摘要翻译： 为了对数字信号进行编码，将其分解成几个子信号（20） 每个子信号通过从M个编码技术Ci中获取的编码技术进行编码（38）; 并且如此产生的编码比特流在用于接收编码数字信号的文件的第一部分中被输入（40）。 然后模拟与编码技术Ci相关联的每个解码技术Di的每个编码的子信号的应用（48）; 并且当且仅当至少两种不同的解码技术是可接受的，在预定的可能性标准的含义内，为了解码相同的编码的子信号，在文件信息的第二部分中输入（52），使得可以选择， 在解码期间，与用于编码该子信号的编码技术相关联的解码技术。

公开(公告)号：US06583736B1

公开(公告)日：2003-06-24

申请号：US10025618

申请日：2001-12-26

申请人： Thomas G. O'Neill

发明人： Thomas G. O'Neill

IPC分类号： H03M746

CPC分类号： H03M7/40

摘要： A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

摘要翻译： 在编码/解码给定数据块的过程中，实现诸如可变长度编码之类的现有技术编码方案的显着减少的方法包括编目数据中指定的频繁出现值的出现或位置 然后从现有技术的编码方案中排除经常出现的值。

公开(公告)号：US06545615B2

公开(公告)日：2003-04-08

申请号：US09867895

申请日：2001-05-30

申请人： Josephus Arnoldus Henricus Maria Kahlman ,  Kornelis Antonie Schouhamer Immink

发明人： Josephus Arnoldus Henricus Maria Kahlman ,  Kornelis Antonie Schouhamer Immink

IPC分类号： H03M746

CPC分类号： H03M5/14 ,  G11B20/1426 ,  H03M5/145

摘要： In a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal the bitstream of the source signal is divided into n-bit source words. The device comprises converting means adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for at least most of the n-bit source words is parity preserving and/or parity inverting, where m>n≧1. The converting means comprise memory means which contain for each n-bit source word a number of m-bit channel words, arranged in coding states, and a corresponding state number, indicating the state for a next m-bit channel word. After each block of source words q dc-control sourcebits are added, which are converted into r dc-control channelbits, independent of the conversion of a following source word.

摘要翻译： 在用于将二进制源信号的数据位流编码为二进制信道信号的数据位流的设备中，源信号的比特流被划分为n位源字。 该装置包括转换装置，其适于将p个连续的n位源字块转换为p个连续m位信道字的相应块，使得至少大部分n位源字的转换是奇偶校验保持， /或奇偶校验反转，其中m> n> = 1。 转换装置包括存储器装置，其为每个n位源字包含以编码状态布置的多个m位通道字，以及相应的状态号，指示下一个m位通道字的状态。 在每个源字块之后，添加直流控制源比特，转换成直流控制通道，独立于以下源字的转换。

公开(公告)号：US06188337B1

公开(公告)日：2001-02-13

申请号：US09323490

申请日：1999-06-01

申请人： Emina Soljanin

发明人： Emina Soljanin

IPC分类号： H03M746

CPC分类号： H04L25/4908

摘要： A 16B/18B low disparity code is described. The 16-bit input word is split into two bytes, i.e., into two 8-bit words, and each byte is mapped to a 9-bit word. The image of each input byte under the mapping depends at least in part on its disparity, and also in some cases on the disparity of the other word. Certain of the images under the mapping are then inverted. The decision whether to invert an image depends, at least in part, on the running digital sum (RDS) of the output. The RDS is the sum of all 1's in the data stream from its beginning (or from a designated starting point). Significantly, all possible input words are grouped, by disparity, into four categories. The rule for mapping of input words is different for each of the four categories.

摘要翻译： 描述了16B / 18B低差异码。 16位输入字分为两个字节，即分成两个8位字，每个字节映射到一个9位字。 映射下的每个输入字节的图像至少部分取决于其差异，并且在某些情况下还取决于另一个字的差异。然后映射下的图像的维数被反转。 是否反转图像的决定至少部分取决于输出的运行数字和（RDS）。 RDS是从其开始（或从指定起点）开始的数据流中的所有1的总和。值得注意的是，所有可能的输入字由差异分组成四个类别。 输入字的映射规则对于四个类别中的每一个都是不同的。

公开(公告)号：US06781528B1

公开(公告)日：2004-08-24

申请号：US10280148

申请日：2002-10-24

申请人： Chien-Hsin Lin ,  Mitchell Oslick ,  Mushtaq Sarwar

发明人： Chien-Hsin Lin ,  Mitchell Oslick ,  Mushtaq Sarwar

IPC分类号： H03M746

CPC分类号： H03M7/46 ,  G06F9/30025 ,  G06F9/30036

摘要： Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value immediately preceding the corresponding element in the first list; and outputting the plurality of run values into a second vector register; where the above operations are performed in response to the microprocessor receiving the single instruction.

摘要翻译： 使用向量处理单元进行游程长度编码的方法和装置。 在本发明的一个方面，微处理器响应于微处理器接收单个指令而执行的方法包括：从第一向量寄存器接收多个元素的第一列表; 生成分别针对第一列表元素的多个运行值，所述多个运行值中的至少一个运行值指示紧接在第一列表中的相应元素之前的第一值的连续元素的数量; 并将所述多个运行值输出到第二向量寄存器中; 其中响应于微处理器接收到单个指令执行上述操作。

公开(公告)号：US06574773B1

公开(公告)日：2003-06-03

申请号：US09523922

申请日：2000-03-09

申请人： Stephen A. Turk ,  Christopher P. Zook

发明人： Stephen A. Turk ,  Christopher P. Zook

IPC分类号： H03M746

CPC分类号： G11B20/1426 ,  G11B2020/1434 ,  H03M5/145

摘要： A cost-effective high-throughput enumerative encoder is disclosed for encoding m-bit input datawords in an input data stream into n-bit output codewords in an encoded output data stream for use in a communication channel. The enumerative encoder comprises an input buffer for storing a plurality of bits in the input data stream, and a plurality of segmented compare tables for encoding the bits stored in the input buffer into the encoded output data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis. A cost-effective high-throughput enumerative decoder is also disclosed for decoding n-bit input codewords in a received data stream into m-bit output datawords in a decoded data stream for use in a communication channel. The enumerative decoder comprises an input buffer for storing a plurality of bits in the received data stream, and a plurality of segmented compare tables for decoding the bits stored in the input buffer into the decoded data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis.

摘要翻译： 公开了一种经济有效的高吞吐量枚举编码器，用于将输入数据流中的m位输入数据字编码为用于通信信道的编码输出数据流中的n位输出码字。 枚举编码器包括用于存储输入数据流中的多个位的输入缓冲器和用于将存储在输入缓冲器中的位编码为编码输出数据流的多个分段比较表，其中每个分段比较表表示段 一个完整的比较表的枚举格子。 还公开了一种经济有效的高吞吐量枚举解码器，用于将接收到的数据流中的n比特输入码字解码为用于通信信道的解码数据流中的m位输出数据字。 枚举解码器包括用于存储接收数据流中的多个位的输入缓冲器和用于将存储在输入缓冲器中的位解码为解码数据流的多个分段比较表，其中每个分段比较表表示 一个枚举网格的完整比较表。

公开(公告)号：US06353912B1

公开(公告)日：2002-03-05

申请号：US09193698

申请日：1998-11-17

申请人： Masaki Uchida

发明人： Masaki Uchida

IPC分类号： H03M746

CPC分类号： H03M5/145

摘要： An encoding circuit for use with a digital signal transmitting apparatus and a digital signal recording/reproducing apparatus encodes a 16-bit information word into a 18-bit code word by trellis encoding method in the condition that the range of the variation of the ADS is limited in such a manner that the 18-bit code word is composed of a combination of 9-bit sub-code words. Thus, while the channel line density and the circuit scale are being suppressed from increasing, the transmission rate of user data can be improved.

摘要翻译： 一种与数字信号发送装置和数字信号记录/再现装置一起使用的编码电路，在ADS变化范围为16位的条件下，通过网格编码方法将16位信息字编码为18位码字 受限于18位代码字由9位子代码字的组合组成。 因此，尽管抑制了通道线密度和电路规模的增加，但是可以提高用户数据的传输速率。

公开(公告)号：US06191710B1

公开(公告)日：2001-02-20

申请号：US09222956

申请日：1998-12-30

申请人： Kenneth R. Waletzki

发明人： Kenneth R. Waletzki

IPC分类号： H03M746

CPC分类号： H03M7/3084 ,  H03M7/30

摘要： A system for compressing and decompressing a data pattern of data bits, so as to obtain a highly compressed data record. In accordance with embodiments of the invention, a group of candidate numbers is provided with each number comprising a sequence of statistically random bits. Bits of a subject data pattern are compared with bits of each candidate of the group of numbers to find a largest sequence of bits of the subject data pattern which match a sequence of bits within any one of the group of candidate numbers. Stored are all of: the data pattern except the matched bits, information designating the candidate number providing a largest matching sequence of bits, locations of the matched bits in the subject data pattern and in the candidate number, and a number encoding a number of the matched bits.

摘要翻译： 一种用于压缩和解压缩数据位的数据模式的系统，以便获得高度压缩的数据记录。 根据本发明的实施例，提供一组候选号码，每个号码包括一系列统计随机比特。 将主题数据模式的比特与该组数字的每个候选的比特进行比较，以找到与候选号码组中的任一组中的任一个中的比特序列匹配的主题数据模式的最大比特序列。 存储的全部是：匹配比特之外的数据模式，指定提供比特的最大匹配序列的候选号码，对象数据模式中的匹配比特的位置和候选号码的信息，以及编码 匹配位。