公开(公告)号：US12119928B2

公开(公告)日：2024-10-15

申请号：US17989117

申请日：2022-11-17

申请人： Dolby Laboratories Licensing Corporation

发明人： Mingchao Yu ,  Mark Craig Reed

IPC分类号： H04L1/00 ,  H04L12/40 ,  H04L67/60 ,  G06F9/48 ,  G06F13/37

CPC分类号： H04L1/0041 ,  H04L1/0033 ,  H04L1/0045 ,  G06F9/4881 ,  G06F13/37 ,  H04L12/4015 ,  H04L67/60

摘要： Systems and methods to transmit data over multiple communication channels in parallel with forward error correction. Original packets are evenly distributed to the channels as the initial systematically channel-encoded packets. Subsequent channel-encoded packets are configured to be linearly independent of their base sets of channel-encoded packets, where a base set for a subsequent channel-encoded packet includes those scheduled to be transmitted before the subsequent packet in the same channel as the subsequent packet, and optionally one or more initial packets from other channels. The compositions of the sequences of the encoded packets can be predetermined without the content of the packets; and the channel-encoded packets can be generated from the original packets on-the-fly by the transmitters of the channels during transmission. When a sufficient number of packets have been received via the channels, a recipient may terminate their transmissions.

公开(公告)号：US12001365B2

公开(公告)日：2024-06-04

申请号：US16922623

申请日：2020-07-07

申请人： Apple Inc.

发明人： Marc A. Schaub ,  Roy G. Moss

IPC分类号： G06F9/30 ,  G06F9/50 ,  G06F9/54 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37

CPC分类号： G06F13/37 ,  G06F9/30069 ,  G06F9/5022 ,  G06F9/544 ,  G06F13/1642 ,  G06F13/28

摘要： Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.

公开(公告)号：US11947470B2

公开(公告)日：2024-04-02

申请号：US17244332

申请日：2021-04-29

申请人： Lawrence Livermore National Security, LLC

发明人： Robert Matthew Panas

IPC分类号： G05B13/02 ,  G02B26/08 ,  G06F13/12 ,  G06F13/37 ,  G06F15/82

CPC分类号： G06F13/126 ,  G02B26/0833 ,  G05B13/021 ,  G06F13/37 ,  G06F15/825

摘要： A system is disclosed for controlling controllable elements of an external component. The system uses a state translator subsystem (“STS”) which receives a state command from an external subsystem. The STS has at least one module for processing the state command and generating operational commands, in parallel, over a first plurality of channels, to control the elements of the external component. A programmable calibration command translation layer subsystem (“PCCTL”) uses the operational commands to generate granular level commands for controlling the elements, and to transmit the granular level commands over a second plurality of channels. A subsystem is coupled between the PCCTL and the elements, which receives the commands from the PCCTL and uses the commands to generate final output commands, which are applied in parallel, over a third plurality of channels, to the elements.

公开(公告)号：US20240079126A1

公开(公告)日：2024-03-07

申请号：US18387585

申请日：2023-11-07

申请人： Autonomix Medical. Inc.

发明人： Landy Toth ,  Siu Bor Lau

IPC分类号： G16H40/63 ,  A61B5/00 ,  A61B5/01 ,  A61B5/145 ,  A61B5/30 ,  A61M25/00 ,  G06F3/00 ,  G06F13/14 ,  G06F13/37 ,  G06F13/38 ,  H04L9/40 ,  H04L12/54 ,  H04Q11/04

CPC分类号： G16H40/63 ,  A61B5/01 ,  A61B5/14503 ,  A61B5/30 ,  A61B5/6852 ,  A61M25/00 ,  G06F3/00 ,  G06F13/14 ,  G06F13/37 ,  G06F13/38 ,  H04L12/56 ,  H04L63/0823 ,  H04Q11/04 ,  A61B2090/064

摘要： A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

公开(公告)号：US11782834B2

公开(公告)日：2023-10-10

申请号：US17692170

申请日：2022-03-11

申请人： ARTERIS, INC.

发明人： Boon Chuan

IPC分类号： G06F12/08 ,  G06F9/48 ,  G06F13/37 ,  G06F12/0817

CPC分类号： G06F12/0828 ,  G06F9/4881 ,  G06F13/37 ,  G06F2212/621

摘要： In a network-on-chip (NoC) interconnect connected to one or more agents with multiple input ports, one or more switches are provided with a round robin arbiter constructed to use representations of the input ports and, in some embodiments, the current round robin state, as thermometer codes. By using thermometer code to represent port information, the correspondence to the current input and the current state to be granted can be rapidly determined through a simple two-step AND and XOR operations. With such a simple logical procedure, the number of steps to make the determination, and therefore the energy required, can be reduced by log 2(n) steps or up to 43%. Using thermometer code reduces the number of computations required. Hence, the number of logic circuit elements required to carry out the calculation is reduced, shrinking the floorplan area needed for the arbiter.

公开(公告)号：US11509417B2

公开(公告)日：2022-11-22

申请号：US16750185

申请日：2020-01-23

申请人： Dolby Laboratories Licensing Corp.

发明人： Mingchao Yu ,  Mark Craig Reed

IPC分类号： H04L1/00 ,  G06F13/37 ,  H04L12/40 ,  G06F9/48 ,  H04L67/60

摘要： Systems and methods to transmit data over multiple communication channels in parallel with forward error correction. Original packets are evenly distributed to the channels as the initial systematically channel-encoded packets. Subsequent channel-encoded packets are configured to be linearly independent of their base sets of channel-encoded packets, where a base set for a subsequent channel-encoded packet includes those scheduled to be transmitted before the subsequent packet in the same channel as the subsequent packet, and optionally one or more initial packets from other channels. The compositions of the sequences of the encoded packets can be predetermined without the content of the packets; and the channel-encoded packets can be generated from the original packets on-the-fly by the transmitters of the channels during transmission. When a sufficient number of packets have been received via the channels, a recipient may terminate their transmissions.

公开(公告)号：US20220350764A1

公开(公告)日：2022-11-03

申请号：US17811209

申请日：2022-07-07

申请人： STMicroelectronics S.r.l.

发明人： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC分类号： G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

公开(公告)号：US11232055B2

公开(公告)日：2022-01-25

申请号：US16942056

申请日：2020-07-29

申请人： Schneider Electric Industries SAS

发明人： Felipe Castillo Buenaventura ,  Pablo Garcia Viano ,  Gregory Molina ,  Loïc Caseras ,  Benjamin Plessis

IPC分类号： G06F13/362 ,  G06F11/07 ,  G06F11/30 ,  G06F13/37

摘要： A method for addressing a slave device in a network system comprising a master device and a plurality of slave devices. The slave devices have a common default address in an unaddressed state and the master device and the plurality of slave devices are connected in chain via a power line and a communication line,
wherein each slave device is indexed by an index greater than or equal to 1, the slave device of index 1 being connected to the master device,
wherein, to address the slave device of index k, k being equal to or greater than 2, the method first instructs the slave device of index k−1 to activate the power supply of the slave device of index k via the power line, and then, it sends, to the common default address on the communication line, a command to change the common default address of the slave device of index k to a unique address of index k. Therefore, at each iteration, there is only one unaddressed slave device in the network.

公开(公告)号：US20220012201A1

公开(公告)日：2022-01-13

申请号：US16922623

申请日：2020-07-07

申请人： Apple Inc.

发明人： Marc A. Schaub ,  Roy G. Moss

IPC分类号： G06F13/37 ,  G06F13/28 ,  G06F13/16 ,  G06F9/54 ,  G06F9/50 ,  G06F9/30

摘要： Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.

公开(公告)号：US11030148B2

公开(公告)日：2021-06-08

申请号：US15945477

申请日：2018-04-04

申请人： Lawrence Livermore National Security, LLC

发明人： Robert Panas

IPC分类号： G06F13/37 ,  G06F15/82 ,  G05B13/02 ,  G02B26/08 ,  G06F13/12

摘要： An electronic control system is disclosed for controlling individually controllable elements of an external component. In one embodiment the system may include a state translator subsystem for receiving a state command from an external subsystem. The state translator subsystem may have at least one module for processing the state command and generating operational commands for controlling the elements to achieve a desired state or condition. A programmable calibration command translation layer (PCCTL) subsystem may be included which receives and uses the operational commands to generate granular level commands for controlling the elements. A feedback control layer subsystem may be included which applies the granular level commands to the elements, and further modifies the granular level commands as needed to control the elements in closed loop fashion.