公开(公告)号：US20210318852A1

公开(公告)日：2021-10-14

申请号：US16847505

申请日：2020-04-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Seyoung Kim ,  Mingu Kang ,  Kyu-hyoun Kim ,  Seonghoon Woo

IPC分类号： G06F7/44 ,  H03K19/02

摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.

公开(公告)号：US20210026916A1

公开(公告)日：2021-01-28

申请号：US16521294

申请日：2019-07-24

申请人： Facebook, Inc.

发明人： Thomas Mark Ulrich

IPC分类号： G06F17/16 ,  G06F7/44

摘要： A first group of modulo result matrices corresponding to modulo of elements of a first matrix by each of a plurality of moduli is stored. A second group of modulo result matrices corresponding to modulo of elements of a second matrix by each of the plurality of moduli is stored. It is determined whether an element operation of a multiplication of the first matrix with the second matrix can be performed using a first hardware multiplication module rather than a second hardware multiplication module. In response to a determination that the element operation can be performed using the first hardware multiplication module, the element operation is performed using the first hardware multiplication module including by multiplying one or more corresponding elements from the first group of modulo result matrices with one or more corresponding elements from the second group of modulo result matrices.

公开(公告)号：US10664001B2

公开(公告)日：2020-05-26

申请号：US16356435

申请日：2019-03-18

申请人： QUALCOMM Incorporated

发明人： Mohamed Abouzied ,  Rajagopalan Rangarajan ,  Peter Shah

IPC分类号： G06G7/20 ,  G06F7/44 ,  G06F7/552 ,  G05F3/26 ,  H04B17/13 ,  G05F3/24

摘要： A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

公开(公告)号：US10101966B1

公开(公告)日：2018-10-16

申请号：US15478056

申请日：2017-04-03

申请人： ALTERA CORPORATION

发明人： Martin Langhammer

IPC分类号： G06F7/44

摘要： A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

公开(公告)号：US10042605B2

公开(公告)日：2018-08-07

申请号：US15132280

申请日：2016-04-19

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Christian Wiencke ,  Armin Stingl

IPC分类号： G06F7/52 ,  G06F7/44 ,  G06F7/53 ,  G06F7/42

摘要： A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

公开(公告)号：US10037189B2

公开(公告)日：2018-07-31

申请号：US15270153

申请日：2016-09-20

申请人： Altera Corporation

发明人： Martin Langhammer

IPC分类号： G06F7/44 ,  G06F7/487

CPC分类号： G06F7/4876

摘要： The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point multiplication operation. Inter-block signaling circuits may generate rounding information and propagate the rounding information together with partial product results from a current specialized processing block to another specialized processing block.

公开(公告)号：US09836279B2

公开(公告)日：2017-12-05

申请号：US14865359

申请日：2015-09-25

申请人： ARM LIMITED

发明人： David Raymond Lutz

IPC分类号： G06F7/44 ,  G06F7/487 ,  G06F5/01

CPC分类号： G06F7/4876 ,  G06F5/012

摘要： An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.

公开(公告)号：US20170060943A1

公开(公告)日：2017-03-02

申请号：US15252306

申请日：2016-08-31

申请人： Ningbo University

发明人： Pengjun WANG ,  Kangping LI ,  Huihong ZHANG

IPC分类号： G06F17/30 ,  G06F7/44

CPC分类号： G06F17/30442 ,  G06F7/44

摘要： A method for optimizing an area of a ternary FPRM circuit using population migration algorithm, the method including: 1) establishing an area estimation model of the ternary FPRM circuit; 2) establishing a corresponding relationship between the ternary FPRM circuit and population migration algorithm; 3) setting an attraction function for calculating the attraction of the population location in population migration algorithm; 4) setting relevant parameters of population migration algorithm; and 5) employing population migration algorithm to calculate and obtain the greatest attractive site and the greatest attraction.

摘要翻译： 一种使用人口迁移算法优化三元FPRM电路面积的方法，该方法包括：1）建立三元FPRM电路的面积估计模型; 2）建立三元FPRM电路与人口迁移算法的对应关系; 3）设定人口迁移算法中人口定位吸引力的吸引力函数; 4）设定人口迁移算法的相关参数; 和5）采用人口迁移算法计算和获得最大的吸引力地点和最大的吸引力。

公开(公告)号：US20150363168A1

公开(公告)日：2015-12-17

申请号：US14303225

申请日：2014-06-12

申请人： Bank of America Corporation

发明人： Steven A. Guccione

IPC分类号： G06F7/44 ,  G06F5/01

CPC分类号： G06F7/523 ,  G06F7/5306

摘要： A pipelined multiply-scan circuit that may be used for high-performance computing. The pipelined multiply-scan circuit may comprise dedicated hardware configured to execute one or more sub-calculations associated with a pipelined multiply-scan process utilizing one or more serially-connected left-shift modules, and one or more serially-connected adder.

摘要翻译： 可用于高性能计算的流水线式乘法扫描电路。 流水线式乘法扫描电路可以包括被配置为执行与使用一个或多个串行连接的左移模块以及一个或多个串联连接的加法器的流水线乘法扫描过程相关联的一个或多个子计算的专用硬件。

公开(公告)号：US09190956B2

公开(公告)日：2015-11-17

申请号：US13697824

申请日：2011-05-13

申请人： Hartmut G. Roskos ,  Alvydas Lisauskas ,  Sebastian Boppel

发明人： Hartmut G. Roskos ,  Alvydas Lisauskas ,  Sebastian Boppel

IPC分类号： G06F7/44 ,  H03D7/12

CPC分类号： H03D7/125

摘要： A sub-harmonic electronic mixer has at least one field effect transistor (FET) having a gate, source, and drain; and a useful signal input at a useful frequency; and a local oscillator input. The input receives the oscillator signal at a frequency being an integral fraction of the useful frequency, plus or minus a mixing frequency to provide a signal output. A gate of the FET and/or the drain and/or the source receives the useful signal to generate a gate-source voltage and/or a drain-source voltage whereby the gate receives the local oscillator signal to generate a gate-source voltage, and the drain or a source receives the local oscillator signal to generate a drain-source voltage. A phase shift is introduced between the signal received at the gate and the signal received at the drain or source of the FET.

摘要翻译： 子谐波电子混合器具有至少一个具有栅极，源极和漏极的场效应晶体管（FET）; 并在有用的频率输入有用的信号; 和本地振荡器输入。 该输入以与有用频率成正比的频率接收振荡器信号，加或减一个混频以提供信号输出。 FET和/或漏极和/或源极的栅极接收有用信号以产生栅极 - 源极电压和/或漏极 - 源极电压，由此栅极接收本地振荡器信号以产生栅极 - 源极电压， 并且漏极或源接收本地振荡器信号以产生漏极 - 源极电压。 在栅极接收的信号和在FET的漏极或源极处接收的信号之间引入相移。