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公开(公告)号：US11640333B2
公开(公告)日：2023-05-02
申请号：US17501890
申请日：2021-10-14
IPC分类号： G06F11/10 , G11C29/52 , H03M13/35 , H03M13/11 , H03M13/00 , G11C29/02 , H03M13/15 , G11C29/04
摘要： Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
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公开(公告)号：US20230081358A1
公开(公告)日：2023-03-16
申请号：US18056587
申请日：2022-11-17
申请人： Kioxia Corporation
摘要： According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
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公开(公告)号：US20230080339A1
公开(公告)日：2023-03-16
申请号：US17991799
申请日：2022-11-21
申请人： Silicon Motion, Inc.
发明人： Tsung-Chieh Yang
摘要： An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
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公开(公告)号：US11606105B2
公开(公告)日：2023-03-14
申请号：US17529193
申请日：2021-11-17
发明人： Jun Tao , Niang-Chu Chen
摘要： Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
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公开(公告)号：US11601139B2
公开(公告)日：2023-03-07
申请号：US16680738
申请日：2019-11-12
发明人： Manish Goel , Yuming Zhu
摘要： Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.
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公开(公告)号：US11599285B2
公开(公告)日：2023-03-07
申请号：US17321189
申请日：2021-05-14
发明人： Jon C. R. Bennett
摘要： A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
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公开(公告)号：US20230062952A1
公开(公告)日：2023-03-02
申请号：US17901159
申请日：2022-09-01
申请人： SK hynix Inc.
发明人： Se Ra JEONG , Kyung Hoon KIM , Ji Hwan PARK , Ha Jun JEONG , Jae Hoon CHA
摘要： A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.
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公开(公告)号：US11586540B2
公开(公告)日：2023-02-21
申请号：US17398341
申请日：2021-08-10
发明人： Antonino Mondello , Francesco Tomaiuolo , Salvatore Giove , Pierluca Guarino , Fabio Indelicato , Marco Ruta , Maria Luisa Gambina , Giovanni Nunzio Maria Avenia , Carmela Maria Calafato
IPC分类号： G06F11/00 , G06F12/0811 , G11C29/52 , G06F11/10
摘要： Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.
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公开(公告)号：US11575395B2
公开(公告)日：2023-02-07
申请号：US17317280
申请日：2021-05-11
申请人： Kioxia Corporation
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/29 , G06F11/10 , G11C29/52 , H03M13/00 , H03M13/35 , G06F13/16 , G06F13/40 , H03M13/03
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
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公开(公告)号：US20230031649A1
公开(公告)日：2023-02-02
申请号：US17790244
申请日：2020-09-23
发明人： Zengfa PENG
IPC分类号： G11C29/52 , G11C11/419
摘要： A static random-access memory and a fault detection circuit thereof are provided. The fault detection circuit includes: a bit line coupling circuit, coupled between a first bit line and a second bit line, wherein the bit line coupling circuit is adapted to use a bit line with a lower potential between the first bit line and the second bit line to couple a bit line with a higher potential between the first bit line and the second bit line to a floating low potential in response to performing the data write operation on the memory cell in a test mode by the write circuit; and a fault determining circuit, adapted to, in response to the memory cell being at the test mode, obtain and compare write data and read data corresponding to the write data, to determine whether the SRAM has a Data Retention Fault based on a comparison result.
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