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    Antenna modules and systems, and applications and methods of manufacturing thereof
    2.
    发明授权
    Antenna modules and systems, and applications and methods of manufacturing thereof 有权

    公开(公告)号：US10153560B2

    公开(公告)日：2018-12-11

    申请号：US15836205

    申请日：2017-12-08

    申请人： BEAM SEMICONDUCTOR LTD.

    发明人： Alberto Milano ,  Rafi Popovich ,  Abraham Saad ,  Jacob Reshef

    IPC分类号： H04N5/38 ,  H01Q21/06 ,  H01Q21/00 ,  H01Q21/24 ,  H03B19/10 ,  H01Q19/06 ,  H01Q1/42 ,  H01Q1/52 ,  H01Q3/36

    摘要： Antenna modules and systems, and applications and methods of manufacturing thereof, are described herein. An example radio frequency (RF) signal transmitter includes a data signal port to receive a baseband data signal; a carrier signal port to receive an initial carrier signal; and an antenna module coupled to the signal ports. The antenna module includes: a substrate with a front face that has a phased array of active antenna elements that includes at least two columns of the active antenna elements; and a rear face that has, for each column, a RF signal launcher to receive a RF data signal for the column; and a transmitting module mounted to the rear face. The transmitting module has, for each column of active antenna elements: a combiner to form the RF data signal; and a RF signal port to transmit the RF data signal to the RF signal launcher.

    Frequency multiplier and signal frequency-multiplying method
    3.
    发明授权
    Frequency multiplier and signal frequency-multiplying method 有权
    倍频器和信号倍频法

    公开(公告)号：US08988120B2

    公开(公告)日：2015-03-24

    申请号：US14143204

    申请日：2013-12-30

    申请人： MStar Semiconductor, Inc.

    发明人： Shu-Wei Chu ,  Yao-Chi Wang

    IPC分类号： H03B19/00 ,  H03B19/14 ,  H03B19/10 ,  H03B19/06

    CPC分类号： H03B19/14 ,  H03B19/00 ,  H03B19/06 ,  H03B19/10

    摘要： A frequency multiplier includes a first impedance module, a second impedance module, a first path and a second path. When the first path is conducted, the first impedance module generates a first output signal and the second impedance module generates a second output signal. When the second path is conducted, the first impedance module generates a third output signal and the second impedance module generates a fourth output signal. The first and second paths are not conducted simultaneously. A frequency of a first combination signal generated from the first and third output signals and a frequency of a second combination signal generated from the second and fourth output signals are N times of a frequency of the input signal, where N is a positive rational number.

    摘要翻译： 倍频器包括第一阻抗模块，第二阻抗模块，第一路径和第二路径。 当第一路径被传导时，第一阻抗模块产生第一输出信号，而第二阻抗模块产生第二输出信号。 当第二路径被传导时，第一阻抗模块产生第三输出信号，第二阻抗模块产生第四输出信号。 第一和第二路径不同时进行。 从第一和第三输出信号产生的第一组合信号的频率和从第二和第四输出信号产生的第二组合信号的频率是输入信号的频率的N倍，其中N是正有理数。

    DIGITAL SIGNAL PROCESSING CIRCUIT
    4.
    发明申请
    DIGITAL SIGNAL PROCESSING CIRCUIT 审中-公开
    数字信号处理电路

    公开(公告)号：US20090072870A1

    公开(公告)日：2009-03-19

    申请号：US11959628

    申请日：2007-12-19

    申请人： Hirofumi Inada

    发明人： Hirofumi Inada

    IPC分类号： H03B19/10

    CPC分类号： H03M5/22

    摘要： A digital signal processing circuit performs a predetermined computation processing on input data sequentially input at a first frequency, and generates output data of a second frequency oversampled to n times (n is an integer greater than or equal to 2). A computation processing unit collectively computes m (m is 2≦m≦n) successive output data in output data at n sampling timings after oversampling. A data holding unit holds data at a predetermined sampling timing in the data generated in the computation processing unit. An output data holding unit holds data at m sampling timings to be output. An output data generating unit sequentially outputs m output data obtained by the computation processing unit according to a second frequency.

    摘要翻译： 数字信号处理电路对以第一频率顺序输入的输入数据执行预定的计算处理，并且产生第二频率被过采样到n次的输出数据（n是大于或等于2的整数）。 计算处理单元在过采样之后的n个采样定时处统计计算输出数据中的m（m = 2 <= m <= n）个连续输出数据。 数据保持单元在计算处理单元中生成的数据中以预定的采样定时保持数据。 输出数据保持单元以m个采样定时保存要输出的数据。 输出数据生成单元根据第二频率顺序地输出由计算处理单元获得的m个输出数据。

    Combined controlled oscillator and frequency multiplier
    5.
    发明授权
    Combined controlled oscillator and frequency multiplier 失效
    组合控制振荡器和频率乘法器

    公开(公告)号：US4052673A

    公开(公告)日：1977-10-04

    申请号：US718802

    申请日：1976-08-30

    申请人： Gerald Bernard Herzog

    发明人： Gerald Bernard Herzog

    IPC分类号： H03L7/18 ,  H03B19/00 ,  H03B19/14 ,  H03K7/06 ,  H03L7/099 ,  H03L7/183 ,  H04N5/50 ,  H04B1/04 ,  H03B19/10 ,  H03B25/00 ,  H04B1/28

    CPC分类号： H03L7/183 ,  H03K7/06 ,  H03L7/0995 ,  H04N5/50

    摘要： A voltage controlled oscillator which, for example, may be utilized in a phase locked loop, includes an odd number (n) of cascaded COS-MOS inverter stages with a feedback path coupling the output of the last stage to the input of the first stage to form a ring configuration. The ring configuration oscillates at a frequency f.sub.1 determined by the transconductances of the inverter stages and the shunt capacitances between the stages. Signals comprising impulses of current having frequency components at f.sub.1 and 2f.sub.1 flow through the power supply inputs of each of the stages as they successively are switched from one state to another. A frequency selective impedance path is coupled between a source of power supply voltage and the power supply inputs of each of the stages to develop a second signal having a frequency f.sub.2 equal to a multiple nf.sub.1 or 2nf.sub.1. The voltage applied to the commonly connected power supply inputs may be controlled to control f.sub.1 and, consequently, f.sub.2.