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公开(公告)号：US10855264B1
公开(公告)日：2020-12-01
申请号：US16730132
申请日：2019-12-30
发明人： Cheng Tao , Xiangyu Ji , Yu Chen , Jiaxi Fu , Haiyan Wei
IPC分类号： H03K5/153 , H03K5/1532 , H03F3/45
摘要： A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.
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2.发明授权公开(公告)号：US10778034B2
公开(公告)日：2020-09-15
申请号：US16207848
申请日：2018-12-03
IPC分类号： H03K5/1532 , H02J50/10 , H03K19/20 , H02J50/80 , H03K5/1536 , H03K5/24 , H04B5/00 , H04B5/02 , H03K5/00
摘要： A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.
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公开(公告)号：US20200186062A1
公开(公告)日：2020-06-11
申请号：US16704144
申请日：2019-12-05
申请人： MAGNA CLOSURES INC.
发明人： Luca FANCELLU , Antonio FRELLO , Jacopo FANUCCHI
摘要： A control system for controlling a mechanically commutated direct current electric motor and corresponding method of operation are provided. The control system includes a motor current sensing circuit for sensing a motor current comprising a plurality of ripples due to commutation of the motor and outputting a motor current signal. The control system also includes a controller including a finite state machine unit and is configured to detect the plurality of ripples in the motor current and to determine whether each of the plurality of ripples is a valid ripple using the finite state machine unit. The controller is also configured to count the plurality of ripples determined to be valid using the finite state machine unit and to determine at least one of a motor rotational position and a motor speed of the motor based on a quantity of the plurality of ripples determined to be valid.
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公开(公告)号：US10651841B2
公开(公告)日：2020-05-12
申请号：US16247146
申请日：2019-01-14
IPC分类号： H03K3/00 , H03K17/687 , H03K5/1532 , H03K5/08 , H03K3/0233 , H03K5/24 , H02M1/08 , H03K17/082 , H03K17/16
摘要： An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.
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公开(公告)号：US20190149150A1
公开(公告)日：2019-05-16
申请号：US16247146
申请日：2019-01-14
IPC分类号： H03K17/687 , H02M1/08 , H03K5/24 , H03K5/08 , H03K17/082 , H03K3/0233 , H03K17/16 , H03K5/1532
摘要： An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.
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公开(公告)号：US20190138758A1
公开(公告)日：2019-05-09
申请号：US15808607
申请日：2017-11-09
CPC分类号： G06G7/25 , G01R19/003 , G01R19/04 , H02J7/0077 , H03K5/1532 , H05B33/08
摘要： A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.
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7.发明申请公开(公告)号：US20180337596A1
公开(公告)日：2018-11-22
申请号：US15599596
申请日：2017-05-19
申请人： GLOBALFOUNDRIES INC.
发明人： Wern Ming KOE
IPC分类号： H02M3/07 , H03K5/1532
CPC分类号： H02M3/073 , H03K5/1532
摘要： The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.
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8.发明申请公开(公告)号：US20180287597A1
公开(公告)日：2018-10-04
申请号：US16001682
申请日：2018-06-06
发明人： Vanni Poletto , Andrea Maino
IPC分类号： H03K5/1532 , H03K7/08 , H02P27/08
CPC分类号： H03K5/1532 , H02P7/02 , H02P7/025 , H02P7/04 , H02P27/085 , H03K7/08 , H03K17/165 , H03K17/689
摘要： A ringing peak detector circuit includes an input buffer receives a pair of differential feedback signals indicating a drain-source voltage of the at least one low side electronic switch. The input buffer generates shifted differential feedback signals having a common mode voltage that is equal to approximately one half of the supply voltage. A peak detector circuit is coupled to the input buffer to receive the shifted differential voltage signals. The peak detector circuit detects a peak value of an oscillation on the inductive electric load and to generate an output signal indicating the detected peak value. A circuit generates a control signal based on the detected peak value and a maximum value, with the control signal being applied to the inductive electrical load driver to control switching of the at least one low side switch.
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公开(公告)号：US20180219547A1
公开(公告)日：2018-08-02
申请号：US15636365
申请日：2017-06-28
IPC分类号： H03K17/687 , H03K5/1532 , H03K5/08 , H03K3/0233 , H03K5/24 , H02M1/08
CPC分类号： H03K17/687 , H02M1/08 , H03K3/02337 , H03K5/08 , H03K5/1532 , H03K5/2472 , H03K5/2481 , H03K17/0822 , H03K17/165
摘要： An apparatus includes a voltage divider circuit including a plurality of series- connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.
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公开(公告)号：US20180131356A1
公开(公告)日：2018-05-10
申请号：US15632238
申请日：2017-06-23
发明人： Rahul Karmaker
摘要： The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.
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