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    A NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE
    1.
    发明申请
    A NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE 审中-公开
    多存储体结构的噪声免疫数据路径方案

    公开(公告)号：WO2018075200A1

    公开(公告)日：2018-04-26

    申请号：PCT/US2017/053284

    申请日：2017-09-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： NARASIMHAN, Mukund ,  GUPTA, Sharad Kumar ,  SHANMUGASUNDARAM, Dharaneedharan

    IPC: G11C11/419 ,  G11C7/02

    CPC classification number: G06F13/1689 ,  G11C7/02 ,  G11C7/1087 ,  G11C7/12 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209 ,  G11C2207/2245

    Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.

    Abstract translation: 在本公开的一个方面中，提供了一种装置。 在一个方面，该装置是一种存储装置。 存储装置包括存储器。 存储器包括第一和第二位单元阵列。 存储装置还包括读出放大器。 读出放大器由第一和第二位单元阵列共享。 另外，读出放大器被配置为在读操作期间放大存储在存储器中的数据。 存储器装置还包括写入电路。 写入电路被配置为在写入操作期间将数据写入存储器。 存储装置还包括控制器。 控制器配置为在读操作期间禁用写电路。

    APPARATUS AND METHOD FOR CONTROLLING BOOST CAPACITANCE FOR LOW POWER MEMORY CIRCUITS
    3.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING BOOST CAPACITANCE FOR LOW POWER MEMORY CIRCUITS 审中-公开

    公开(公告)号：WO2018136212A1

    公开(公告)日：2018-07-26

    申请号：PCT/US2017/068570

    申请日：2017-12-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： SINHA, Rakesh Kumar ,  NARASIMHAN, Mukund ,  GUPTA, Sharad Kumar

    IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G11C7/10

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/12

    Abstract: A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.

    PULSE LATCH RESET TRACKING AT HIGH DIFFERENTIAL VOLTAGE
    6.
    发明申请
    PULSE LATCH RESET TRACKING AT HIGH DIFFERENTIAL VOLTAGE 审中-公开
    高差分电压下的脉冲锁存重置跟踪

    公开(公告)号：WO2017120002A1

    公开(公告)日：2017-07-13

    申请号：PCT/US2016/066609

    申请日：2016-12-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： NARASIMHAN, Mukund ,  GUPTA, Sharad Kumar ,  BODA, Veerabhadra Rao

    IPC: G06F1/04 ,  G11C7/22 ,  H03K3/353

    CPC classification number: G11C7/222 ,  G06F1/04 ,  G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/20 ,  H03K3/356173 ,  H03K5/135

    Abstract: A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal (320) in a first power domain (302) and initiate a second clock signal (324) in a second power domain (304) in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit (350) configured to generate a reset signal (322) based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch (306) configured to receive the second clock signal in the second power domain.

    Abstract translation: 提供了一种用于产生内部存储器时钟的方法和装置。 该装置包括被配置为响应于第一时钟信号而在第一电力域（302）中接收第一时钟信号（320）并且在第二电力域（304）中启动第二时钟信号（324）的脉冲发生器。 第一电源域为逻辑操作提供第一电压，并且第二电源域为存储器操作提供第二电压。 该装置包括被配置为基于第一电力域的电压电平生成重置信号（322）的跟踪电路（350）。 重置信号可以被配置为重置第一电力域中的脉冲发生器。 该设备还可以包括锁存器（306），其被配置为在第二电力域中接收第二时钟信号。

    Memory with High-Speed and Area-Efficient Read Path
    7.
    发明申请
    Memory with High-Speed and Area-Efficient Read Path 审中-公开

    公开(公告)号：WO2020237211A1

    公开(公告)日：2020-11-26

    申请号：PCT/US2020/034378

    申请日：2020-05-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： BHASKARAN, Adithya ,  NARASIMHAN, Mukund ,  MOHANTY, Shiba Narayan

    IPC: G11C29/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419 ,  G11C5/14

    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter. A first transistor is coupled between a first output node of the sense amplifier and a first input node to the data latch. A first logic gate is configured to assert a combined sense enable and redundancy shift-off signal in response to an assertion of both a sense enable signal and a redundancy shift-off signal, wherein the first transistor is configured to switch on in response to the assertion of the combined sense enable and redundancy shift-off signal.

    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
    8.
    发明申请
    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT 审中-公开

    公开(公告)号：WO2019070355A1

    公开(公告)日：2019-04-11

    申请号：PCT/US2018/048824

    申请日：2018-08-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： GUPTA, Sharad Kumar ,  RAJ, Pradeep ,  SAHU, Rahul ,  NARASIMHAN, Mukund

    IPC: G11C7/12 ,  G11C11/419

    Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines (BL; BLB) coupled to the memory cell, a multiplexer (404), and a pull-up circuit (418) coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non¬ zero bit line during the write operation and to clamp the non-zero bit line through read pass transistors (rpO, rpbO) of the multiplexer to approximately a power rail voltage (VDD). Thus, the pull-up circuit (418) may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance of a conventional write driver.

    AGING MITIGATION
    10.
    发明申请
    AGING MITIGATION 审中-公开

    公开(公告)号：WO2023014460A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/036199

    申请日：2022-07-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： NARASIMHAN, Mukund ,  ADE, Murali Krishna ,  ARUL DIRAVIYAM, Arun David ,  GUPTA, Mayank ,  ANDREEV, Boris Dimitrov

    IPC: H03K19/00

    Abstract: Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

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