公开(公告)号：WO2004003970A9

公开(公告)日：2004-07-15

申请号：PCT/US0319085

申请日：2003-06-18

Applicant: SEMEQUIP INC ,  KRULL WADE A ,  JACOBSON DALE C

Inventor： KRULL WADE A ,  JACOBSON DALE C

IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/425

CPC classification number: H01L21/2255 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/32155 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

Abstract translation: 提出了一种用于制造半导体器件的栅极的方法，使得栅极耗尽的效果最小化。 该方法包括双重沉积工艺，其中第一步是通过离子注入非常重的掺杂的非常薄的层。 具有用于掺杂的相关联的离子注入的第二沉积完成栅电极。 通过双沉积工艺，可以最大化在栅电极/栅极电介质界面处的掺杂，同时最小化栅极电介质的硼渗透的风险。 该方法的进一步发展包括利用漏极延伸和源极/漏极注入作为栅极掺杂注入的优点以及偏移两个图案以产生非对称器件的优点的两个栅极电极层的图案化。 还提供了一种方法，用于通过掺杂剂从包含在电介质层中的注入层扩散到半导体表面中，在半导体衬底中形成浅结。 此外，离子注入层除了预期的掺杂剂物质之外还具有第二注入物质，例如氢，其中所述物质增强了介电层中掺杂剂的扩散性。

公开(公告)号：WO2008128039A2

公开(公告)日：2008-10-23

申请号：PCT/US2008060029

申请日：2008-04-11

Applicant: SEMEQUIP INC ,  KRULL WADE A ,  JACOBSON DALE C ,  SEKAR KARUPPANAN ,  HORSKY THOMAS N

Inventor： KRULL WADE A ,  JACOBSON DALE C ,  SEKAR KARUPPANAN ,  HORSKY THOMAS N

IPC: A61K38/17

CPC classification number: H01L21/26513 ,  H01J2237/006 ,  H01J2237/31701 ,  H01L21/26506 ,  H01L21/2658

Abstract: A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such as a carbon cluster ion, wherein the dopant ion is implanted into the amorphous layer created by the co-implant in order to reduce defects in the crystalline structure, thus reducing the leakage current and improving performance of the semiconductor junctions. Dopant ion compounds of the form A n H x +

Abstract translation: 公开了一种半导体制造方法，其中通过注入从电离分子形成的离子束来实现掺杂，更具体地说，涉及一种方法，其中将分子和簇掺杂剂离子注入到具有和不具有非共注入 掺杂簇离子，例如碳簇离子，其中将掺杂剂离子注入由共注入产生的非晶层中，以减少晶体结构的缺陷，从而减少漏电流并改善半导体结的性能 。 形式如下的掺杂离子化合物：H

公开(公告)号：WO2004003970A3

公开(公告)日：2004-06-03

申请号：PCT/US0319085

申请日：2003-06-18

Applicant: SEMEQUIP INC ,  KRULL WADE A ,  JACOBSON DALE C

Inventor： KRULL WADE A ,  JACOBSON DALE C

IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/425

CPC classification number: H01L21/2255 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/32155 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

Abstract translation: 提出了一种用于制造半导体器件的栅极的方法，使得栅极耗尽的影响最小化。 该方法包括双沉积工艺，其中第一步是非常薄的层，其通过离子注入非常严重地掺杂。 第二次沉积（用于掺杂的相关离子注入）完成了栅电极。 利用双沉积工艺，可以最大化栅电极/栅极介电界面处的掺杂，同时最小化硼渗透栅极电介质的风险。 该方法的进一步发展包括利用漏极扩展和源极/漏极注入作为栅极掺杂注入以及偏移这两个图案以创建不对称器件的优点，对两个栅极电极层进行构图。 还提供了一种方法，用于通过将掺杂剂从包含在介电层内的注入层扩散到半导体表面中来在半导体衬底中形成浅结。 此外，除了预期的掺杂剂物质之外，离子注入层还提供有第二注入物质，例如氢，其中所述物质增强了介质层中掺杂剂的扩散性。

公开(公告)号：WO2007070321A3

公开(公告)日：2007-11-29

申请号：PCT/US2006046651

申请日：2006-12-06

Applicant: SEMEQUIP INC ,  KRULL WADE A ,  HORSKY THOMAS N

Inventor： KRULL WADE A ,  HORSKY THOMAS N

IPC: H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1 ) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C-IeHx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or BioHx+. Upon subsequent annealing and activation, the boron diffusion is reduced, due to the gettering of interstitial defects by the carbon atoms.

Abstract translation: 公开了一种方法，其包括将碳簇植入衬底中，以便在集成电路中制造PMOS晶体管结构中衬底掺杂硼和磷时改善晶体管结的特性。 这种新方法有两个过程：（1）USJ形成的扩散控制; 和（2）应力工程的高剂量碳植入。 USJ形成的扩散控制结合PMOS中的源极/漏极结构的硼或浅硼簇注入来证明。 更具体地，首先，将簇碳离子（例如C-IeHx +）以与随后的硼植入物大致相同的剂量注入源极/漏极区域; 随后是浅硼，硼簇，磷或磷簇离子注入以形成源极/漏极延伸，优选使用硼氢化簇，例如B18Hx +或BioHx +。 随后的退火和活化，由于碳原子吸收间隙缺陷，硼扩散减少。