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    OXYGEN-DOPING FOR NON-CARBON RADICAL-COMPONENT CVD FILMS
    1.
    发明申请
    OXYGEN-DOPING FOR NON-CARBON RADICAL-COMPONENT CVD FILMS 审中-公开
    用于非碳离子组分CVD膜的氧气掺杂

    公开(公告)号：WO2011068652A2

    公开(公告)日：2011-06-09

    申请号：PCT/US2010/056401

    申请日：2010-11-11

    Applicant: APPLIED MATERIALS, INC. ,  INGLE, Nitin, K. ,  MALLICK, Abhijit Basu ,  SOLIS, Earl Osman ,  KOVARSKY, Nicolay ,  LYUBIMOVA, Olga

    Inventor： INGLE, Nitin, K. ,  MALLICK, Abhijit Basu ,  SOLIS, Earl Osman ,  KOVARSKY, Nicolay ,  LYUBIMOVA, Olga

    IPC: H01L21/3115 ,  H01L21/316 ,  H01L21/318 ,  H01L21/205

    CPC classification number: C23C16/308 ,  C23C16/402 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/56 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32449

    Abstract: Methods of forming silicon oxide layers are described. The methods include the steps of concurrently combining both a radical precursor and a radical-oxygen precursor with a carbon-free silicon-containing precursor. One of the radical precursor and the silicon-containing precursor contain nitrogen. The methods result in depositing a silicon-oxygen-and-nitrogen-containing layer on a substrate. The oxygen content of the silicon-oxygen-and-nitrogen-containing layer is then increased to form a silicon oxide layer which may contain very little nitrogen. The radical-oxygen precursor and the radical precursor may be produced in separate plasmas or the same plasma. The increase in oxygen content may be brought about by annealing the layer in the presence of an oxygen-containing atmosphere and the density of the film may be increased further by raising the temperature even higher in an inert environment.

    Abstract translation: 描述形成氧化硅层的方法。 所述方法包括同时将自由基前体和自由基 - 氧前体与无碳的含硅前体同时组合的步骤。 自由基前体和含硅前体之一含有氮。 该方法导致在衬底上沉积含硅 - 氧和氮的层。 然后，使含硅氧含氮层的氧含量增加，形成可能含有非常少的氮的氧化硅层。 自由基 - 氧前体和自由基前体可以在分离的等离子体或相同的等离子体中产生。 氧含量的增加可以通过在含氧气氛的存在下退火层而实现，并且通过在惰性环境中更高的温度升高可以进一步提高膜的密度。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A MOS TRANSISTOR
    3.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A MOS TRANSISTOR 审中-公开
    制造包含MOS晶体管的半导体器件的方法

    公开(公告)号：WO9965070A3

    公开(公告)日：2000-04-27

    申请号：PCT/IB9901003

    申请日：1999-06-03

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

    Inventor： SCHMITZ JURRIAAN ,  WOERLEE PIERRE H

    IPC: H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/31155

    Abstract: The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (1A) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.

    Abstract translation: 本发明涉及制造（水平）MOST的方法，例如在（BI）CMOS IC中使用的MOST。 在栅电极（2）的任一侧，位于栅极氧化物（1A）上方的硅衬底（10,11）的表面在源（3）的位置处设置有电介质层（1B） 并形成漏极（4），该介电层包括要作为起始层形成的热氧化物层（1B）。 源极（3）和/或漏极（4）设置有LDD区域（3A，4A），源极（3）和漏极（4）的其余部分（3B，4B）由离子注入 （I1）掺杂原子到硅衬底（10,11）中。 以这种方式获得的MOST仍然受到所谓的短沟道效应的影响，导致阈值电压对栅电极（2）的长度的实质依赖性，特别是在非常短的栅电极的长度的情况下 （2）。 在根据本发明的方法中，LDD区域（3A，4A）制成如下：在第一步骤中，在第二离子注入（I2）中，将合适的掺杂原子（D）注入电介质层（1B） ，随后在第二步骤中，一部分掺杂原子（D）从电介质层（1B）扩散到硅衬底（10,11）中，由此形成LDD区（3A，4A）。 该方法使得能够获得具有优异性能的MOST，例如与常规制造的MOST（曲线131）相比，阈值电压相对于栅电极（2）长度（曲线130）的平坦轮廓。 该结果以简单且可再现的方式获得。

    BACKSIDE SEMICONDUCTOR GROWTH
    5.
    发明申请
    BACKSIDE SEMICONDUCTOR GROWTH 审中-公开
    背面SEMICONDUCTOR增长

    公开(公告)号：WO2018031175A1

    公开(公告)日：2018-02-15

    申请号：PCT/US2017/041755

    申请日：2017-07-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： GOKTEPELI, Sinan ,  HAMMOND, Richard

    IPC: H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/762

    Abstract: An integrated circuit structure may include a transistor on a front-side semiconductor layer supported by an isolation layer. The transistor is a first source/drain/body region. The integrated circuit structure may also include a raised source/drain/body region coupled to a backside of the first source/drain/body region of the transistor. The transistor is a raised source/drain/body region extending from the backside of the first source/drain/body region toward a backside dielectric layer supporting the isolation layer. The integrated circuit structure may further include a backside metallization coupled to the raised source/drain/body region.

    Abstract translation: 集成电路结构可以包括由隔离层支撑的前侧半导体层上的晶体管。 晶体管是第一源极/漏极/本体区域。 集成电路结构还可以包括耦合到晶体管的第一源极/漏极/体区的背侧的升高的源极/漏极/体区。 晶体管是从第一源极/漏极/本体区的背面朝向支撑隔离层的背面介电层延伸的升高的源极/漏极/本体区。 集成电路结构可以进一步包括耦合到升高的源极/漏极/体区的背面金属化。

    GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR
    7.
    发明申请
    GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR 审中-公开
    场效应晶体管的门结构

    公开(公告)号：WO2009133515A1

    公开(公告)日：2009-11-05

    申请号：PCT/IB2009/051714

    申请日：2009-04-27

    Applicant: NXP B.V. ,  MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    Inventor： MUELLER, Markus ,  BOCCARDI, Guillaume ,  PETRY, Jasmine

    IPC: H01L21/28 ,  H01L21/265 ,  H01L29/51 ,  H01L21/3115

    CPC classification number: H01L21/26506 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/31155 ,  H01L21/32155 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises Al x Si y O z , which has a higher relative dielectric constant value than SiO 2 . A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO 2 -based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO 2 -based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO 2 -based layer to form an Al x Si y O z interfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.

    Abstract translation: 具有栅极结构的场效应晶体管包括位于晶体管沟道区域和栅极叠层的高K电介质层之间的界面层。 界面层包含Al x Se y O z，其比SiO 2具有更高的相对介电常数值。 一种形成场效应晶体管的栅极结构的方法。 该方法包括形成栅极堆叠，其顺序包括：与场效应晶体管的沟道区相邻的基于SiO 2的层; 在SiO 2基层上的高K电介质层; 以及在高K电介质层上的栅电极。 该方法还包括将Al引入SiO 2基层中以在高K电介质层和沟道区之间形成Al x Se y O z界面层。 加热步骤，允许引入通道区域的Al扩散到沟​​道区域内进入界面层。

    A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    10.
    发明申请
    A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和半导体器件的制造方法

    公开(公告)号：WO2004003970A9

    公开(公告)日：2004-07-15

    申请号：PCT/US0319085

    申请日：2003-06-18

    Applicant: SEMEQUIP INC ,  KRULL WADE A ,  JACOBSON DALE C

    Inventor： KRULL WADE A ,  JACOBSON DALE C

    IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/425

    CPC classification number: H01L21/2255 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/32155 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

    Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

    Abstract translation: 提出了一种用于制造半导体器件的栅极的方法，使得栅极耗尽的效果最小化。 该方法包括双重沉积工艺，其中第一步是通过离子注入非常重的掺杂的非常薄的层。 具有用于掺杂的相关联的离子注入的第二沉积完成栅电极。 通过双沉积工艺，可以最大化在栅电极/栅极电介质界面处的掺杂，同时最小化栅极电介质的硼渗透的风险。 该方法的进一步发展包括利用漏极延伸和源极/漏极注入作为栅极掺杂注入的优点以及偏移两个图案以产生非对称器件的优点的两个栅极电极层的图案化。 还提供了一种方法，用于通过掺杂剂从包含在电介质层中的注入层扩散到半导体表面中，在半导体衬底中形成浅结。 此外，离子注入层除了预期的掺杂剂物质之外还具有第二注入物质，例如氢，其中所述物质增强了介电层中掺杂剂的扩散性。

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