公开(公告)号：WO2018052852A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/050995

申请日：2017-09-11

Applicant: ALTERA CORPORATION

Inventor： AYDONAT, Utku ,  LING, Andrew Chaang ,  CHIU, Gordon Raymond ,  O'CONNELL, Shane

IPC: H03H17/02

CPC classification number: G06F7/44 ,  G06F16/901 ,  G06F17/5054

Abstract: Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter using the transformation function. Each intermediate input value is multiplied with a respective intermediate filter value to form intermediate values. These intermediate values are combined with each other using the transformation function to determine one or more output values.

Abstract translation: 用于过滤数据的设备和方法包括使用变换函数来计算来自输入元素的中间输入值。 转换函数至少部分基于滤波器的大小和一些滤波器输出。 使用变换函数从滤波器的滤波器元素计算中间滤波器值。 每个中间输入值与相应的中间滤波器值相乘以形成中间值。 这些中间值使用转换函数相互组合，以确定一个或多个输出值。

公开(公告)号：WO2017095627A1

公开(公告)日：2017-06-08

申请号：PCT/US2016/062095

申请日：2016-11-15

Applicant: XILINX, INC.

Inventor： GANUSOV, Ilya, K. ,  FRAISSE, Henri ,  SIRASAO, Ashish ,  KAVIANI, Alireza, S.

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying (604) duplicate instances (104, 106) of modules in a representation of the circuit design. A processor circuit (702) performs folding operations (610) for at least one pair of the duplicate instances of a module. One instance of the duplicates is removed (612) from the circuit design, and a multiplexer (210) is inserted (614). The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop (1 16) in the remaining instance, a pipelined flip-flop (204) is inserted (616, 618). Connections to a first clock signal in the remaining instance are replaced (624) with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit (216) is inserted (626) to receive the output signal from the first instance and provide concurrent first and second output signals.

Abstract translation: 所公开的用于处理电路设计的方法包括在电路设计的表示中识别（604）模块的重复实例（104,106）。 处理器电路（702）为模块的至少一对重复实例执行折叠操作（610）。 从电路设计中删除（612）重复的一个实例，并插入多路复用器（210）（614）。 多路复用器接收并选择输入信号中的一个到复制实例，并将选择的输入信号提供给其余实例。 对于其余实例中的每个触发器（116），插入流水线触发器（204）（616,618）。 连接到其余实例中的第一时钟信号的连接被替换（624），连接到具有第一时钟信号的两倍频率的第二时钟信号。 一个对准电路（216）被插入（626）以接收来自第一实例的输出信号并提供并发的第一和第二输出信号。

公开(公告)号：WO2017058457A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/049990

申请日：2016-09-01

Applicant: XILINX, INC.

Inventor： AGGARWAL, Rajat ,  WANG, Zhiyong ,  LU, Ruibing ,  DAS, Sabyasachi

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: In one embodiment of the invention, a processor-implemented method is provided for placing and routing a circuit design (102). A first netlist is generated for a circuit design. Placement is performed (108) for the first netlist (106) on a target IC to produce a first placed design (1 10). A set of optimizations are performed (1 12) on the first placed design. The set of optimizations are recorded (1 14) in an optimization history file (1 16). One or more optimizations specified in the optimization history file are performed (1 18/202) on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed (206) for the second netlist on the target IC to produce a second placed design (208) that is different than the first placed design. Nets of the second placed design are routed (210) to produce a placed and routed circuit design.

Abstract translation: 在本发明的一个实施例中，提供了一种用于放置和布线电路设计（102）的处理器实现的方法。 生成电路设计的第一个网表。 对目标IC上的第一网表（106）执行放置（108）以产生第一放置设计（110）。 在首次放置的设计中执行一组优化（112）。 在优化历史文件（116）中记录优化集（114）。 在第一网表上执行在优化历史文件中指定的一个或多个优化（18/202）以产生与第一网表不同的第二网表。 对目标IC上的第二网表执行放置（206），以产生与第一放置设计不同的第二放置设计（208）。 第二放置设计的网络被路由（210）以产生放置和路由的电路设计。

公开(公告)号：WO2015163944A1

公开(公告)日：2015-10-29

申请号：PCT/US2014/069374

申请日：2014-12-09

Applicant: XILINX, INC.

Inventor： KARRAS, Kimon ,  BLOTT, Michaela ,  VISSERS, Kornelis, A.

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources (130), a plurality of shareable logic circuits (120, 122) coupled to the plurality of programmable resources, and a virtualization circuit (150). The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs (132, 134) implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源（130），耦合到多个可编程资源的多个可共享逻辑电路（120,122）和虚拟化电路（150）。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计（132,134）之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。

公开(公告)号：WO2015121713A1

公开(公告)日：2015-08-20

申请号：PCT/IB2014/060372

申请日：2014-04-02

Applicant: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR

Inventor： CHAKRABORTY, Rajat Subhra ,  PALCHAUDHURI, Ayan

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/06

Abstract: Technologies are described to automate design of field programmable gate array (FPGA) circuits, specifically for fast and efficient architectures for large integer adders and counters through direct instantiation of carry chain primitives and lookup tables in circuit description. In some examples, placement of circuits on relatively adjacent slices may be controlled such that the slices are strongly and logically coupled to enable compact placement and thereby contributing to reduced routing delay and FPGA chip area. Design descriptions and constraint files may be automatically generated by a design application providing operand-width scalability with respect to operating frequency of the designed circuit.

Abstract translation: 技术被描述为自动化现场可编程门阵列（FPGA）电路的设计，特别是通过在电路描述中直接实现进位链原语和查找表，为大型整数加法器和计数器提供快速高效的架构。 在一些示例中，可以控制在相对相邻的片上的电路的放置，使得片被强烈和逻辑地耦合以实现紧凑放置，从而有助于降低路由延迟和FPGA芯片面积。 设计描述和约束文件可以由设计应用程序自动生成，该设计应用程序相对于设计的电路的工作频率提供操作宽度可伸缩性。

公开(公告)号：WO2015099799A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/078149

申请日：2013-12-28

Applicant: INTEL CORPORATION

Inventor： OLBRICH, Franz-Wilhelm ,  PLATE, Ralf ,  MATTNER, Thorsten ,  WOELK, Heiko

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/17744 ,  G06F13/4059 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

Abstract: A dynamic interconnect is described herein. The dynamic interconnect includes a transmit module, a receive module, and a multiplexer. Signal changes are detected in a group of transmit channels, and in response to the signal change an output of the multiplexer is switched to the channel where the change occurs.

Abstract translation: 本文描述了动态互连。 动态互连包括发射模块，接收模块和多路复用器。 在一组发送信道中检测信号变化，并且响应于信号改变，多路复用器的输出被切换到发生变化的信道。

公开(公告)号：WO2015048366A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/057579

申请日：2014-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： GAHOI, Anshul ,  SANTHANAGOPAL, Raghavendra ,  BABU, Pradeep, Kumar

IPC: G06F11/263

CPC classification number: G06F11/27 ,  G01R13/28 ,  G01R31/3177 ,  G06F9/44 ,  G06F11/273 ,  G06F17/5027 ,  G06F17/5054

Abstract: In described examples, a test connector is arranged to communicatively couple a design under test (460) to a test fixture. A programmable logic interface (450) is communicatively coupled to the test connector and is arranged to receive a downloadable test bench (454). The downloadable test bench (454) is arranged to apply test vectors from a first set of test vectors (444) to a first test control bus (458). A multiplexer (462) is arranged to selectively couple one of the first test control bus (458) and a second test control bus (464) to a shared test bus (466) that is coupled to the test connector. The second test control bus (464) is arranged to apply test vectors from a second set of test vectors.

Abstract translation: 在所描述的示例中，测试连接器布置成将被测试设计（460）通信地耦合到测试夹具。 可编程逻辑接口（450）通信地耦合到测试连接器并被布置成接收可下载的测试台（454）。 可下载测试台（454）被布置成将来自第一组测试向量（444）的测试向量应用于第一测试控制总线（458）。 复用器（462）布置成选择性地将第一测试控制总线（458）和第二测试控制总线（464）中的一个耦合到耦合到测试连接器的共享测试总线（466）。 第二测试控制总线（464）被布置成从第二组测试向量应用测试向量。

公开(公告)号：WO2015012961A1

公开(公告)日：2015-01-29

申请号：PCT/US2014/040945

申请日：2014-06-04

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： GRAF, Christopher ,  VERRET, Ryan ,  DIGIOVANNI, Joseph ,  KLIPEC, David ,  BLASIG, Dustyn ,  MOTA, Jeronimo ,  PATEL, Kunal ,  HUDSON, Duncan ,  ODOM, Brian

IPC: G06F9/44 ,  G06F17/50 ,  G06F11/273

CPC classification number: G01D11/00 ,  G06F9/4411 ,  G06F11/273 ,  G06F17/5054

Abstract: System and method for extending programmable device functionality while preserving functionality of the device driver and driver IP. User input may be received specifying functionality of custom IP for a programmable measurement device with standard driver IP. The custom IP may be generated accordingly, and may be deployable to the programmable measurement device. During operation the custom IP may communicate directly with the standard driver IP and may provide custom functionality of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement device and the standard device driver.

Abstract translation: 用于扩展可编程设备功能的系统和方法，同时保留设备驱动程序和驱动程序IP的功能。 可以接收用户输入，指定具有标准驱动程序IP的可编程测量设备的定制IP的功能。 可以相应地生成定制IP，并且可以部署到可编程测量设备。 在操作期间，定制IP可以直接与标准驱动器IP通信，并且可以提供可编程测量设备的定制功能，同时在可编程测量设备和标准设备驱动器上保持标准驱动器IP的功能。

公开(公告)号：WO2014120536A3

公开(公告)日：2014-12-24

申请号：PCT/US2014012640

申请日：2014-01-23

Applicant: GEN ELECTRIC

Inventor： HESS DUSTIN DELANY ,  WEISS ADAM ANTHONY ,  FOX JEREMY DAVID

IPC: G06F17/40 ,  G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5054

Abstract: A data acquisition system (DAS) (200) includes a plurality of processors (215/412/413/414) comprising at least one first processor (215) and a plurality of second processors (414). The at least one first processor is configured to receive at least one configuration file (502) and generate at least one measurement data application (506/507) from the at least one configuration file. The DAS also includes a field-programmable gate array (FPGA) (408) coupled to the plurality of processors. The FPGA is configured to receive the at least one measurement data application and allocate at least a portion (413) of one of the FPGA and at least one second processor of the plurality of second processors to calculate measurement data (556/558/562) at least partially based on the at least one measurement data application and an availability of the at least a portion of the FPGA.

Abstract translation: 数据采集​​系统（DAS）（200）包括包含至少一个第一处理器（215）和多个第二处理器（414）的多个处理器（215/412/413/414）。 所述至少一个第一处理器被配置为接收至少一个配置文件（502）并且从所述至少一个配置文件生成至少一个测量数据应用（506/507）。 DAS还包括耦合到多个处理器的现场可编程门阵列（FPGA）（408）。 FPGA被配置为接收至少一个测量数据应用并且分配FPGA中的一个的至少一部分（413）和多个第二处理器中的至少一个第二处理器来计算测量数据（556/558/562） 至少部分基于所述至少一个测量数据应用和所述FPGA的所述至少一部分的可用性。

公开(公告)号：WO2014171977A1

公开(公告)日：2014-10-23

申请号：PCT/US2013/073683

申请日：2013-12-06

Applicant: XILINX, INC.

Inventor： VO, Thao, H.T. ,  GAN, Andy, H. ,  LI, Xiao-Yu ,  KLEIN, Matthew, H.

IPC: H01L25/065 ,  G06F1/32

CPC classification number: H01L25/0652 ,  G06F1/3203 ,  G06F1/324 ,  G06F17/5045 ,  G06F17/5054 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor package includes an interposer (208, 326, 416, 516) and a plurality of integrated circuit (IC) dice (102-108, 232-234, 322-324, 412-414, 512-514) disposed on and intercoupled via the interposer. A first IC die (102, 232, 322, 412, 512) has a clock speed rating that is greater than a clock speed rating of another (104-108, 234, 324, 414, 514) of the IC dice. A plurality of programmable voltage tuners (1 10-1 16, 202-204, 312 & 316, 402-404, 502-504) are coupled to the plurality of IC dice, respectively. A first voltage tuner (1 10, 202, 312, 402, 502) is coupled to the first IC die (102, 232, 322, 412, 512), and the first voltage tuner is programmed to reduce a voltage level of a voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract translation: 半导体封装包括插入器（208,326,416,516）和多个集成电路（IC）芯片（102-108,232-234,322-324,412-414,512-514），其设置在并联上 通过插入器。 第一IC芯片（102,232,322,412,512）的时钟速度额定值大于IC芯片的另一个时钟速度等级（104-108,234,324,414,514）。 多个可编程电压调谐器（110-116,202-204,312和316,402-404,502-504）分别耦合到多个IC芯片。 第一电压调谐器（110,202,312,402,502）耦合到第一IC管芯（102,232,312,412,512），并且第一电压调谐器被编程以降低电压的电压电平 输入到第一电压调谐器并将降低的电压输出到第一IC芯片。