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706 条记录 (耗时 0.021 秒)

    CMOS STANDARD CELL STRUCTURE WITH LOWER DATA DEPENDENCE OF THE STATIC POWER CONSUMPTION
    1.
    发明申请
    CMOS STANDARD CELL STRUCTURE WITH LOWER DATA DEPENDENCE OF THE STATIC POWER CONSUMPTION 审中-公开

    公开(公告)号：WO2023057795A1

    公开(公告)日：2023-04-13

    申请号：PCT/IB2021/059200

    申请日：2021-10-07

    申请人： CESKE VYSOKE UCENI TECHNICKE V PRAZE

    发明人： BELOHOUBEK, Jan ,  FISER, Petr ,  SCHMIDT, Jan

    IPC分类号： H03K19/00 ,  G06F21/75 ,  H04L9/00 ,  G11C7/24 ,  G06F21/755 ,  G09C1/00 ,  G11C11/412 ,  H03K19/0013 ,  H04L9/003

    摘要： The PMOS block (104) is connected between the virtual supply node (102) and output (101). The NMOS block (105) is connected between the virtual ground node (103) and output (101). The input of the balancing inverter chain (200, 300, 400) is connected to the output O (101). The balancing inverter chain is composed of at least one inverter and the output of the chain is the output (Y) of the structure. The static CMOS circuit (100) is supplemented with any combination of the following circuits. The virtual supply node (102) is connected to the supply rail by a serial P-type transistor (111), which gate (G), is connected to the ground rail. The virtual ground node (103) is connected to the ground rail by the serial N-type transistor (112), which gate (G) is connected to the supply rail. The virtual supply node (102) is connected to the output (101) by the complementary P-type transistor (121). The virtual ground node (103) is connected to the output (101) by the N-type complementary transistor (122).

    VARIABLE CURRENT DRIVE FOR ISOLATED GATE DRIVERS
    3.
    发明申请
    VARIABLE CURRENT DRIVE FOR ISOLATED GATE DRIVERS 审中-公开

    公开(公告)号：WO2022119835A1

    公开(公告)日：2022-06-09

    申请号：PCT/US2021/061196

    申请日：2021-11-30

    申请人： SKYWORKS SOLUTIONS, INC.

    发明人： TESU, Ion C. ,  HECKROTH, James E. ,  MASTOVICH, Stefan N. ,  WILSON, John N. ,  PENTAKOTA, Krishna ,  IRELAND, Michael ,  RIDSDALE, Greg ,  JACKSON, Lyric

    IPC分类号： H03K17/687 ,  H03K19/00 ,  H02M1/08

    摘要： A method for driving a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. In the first phase, the second parameter is a time elapsed from a start of the first phase. The method includes providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process. The method includes transitioning from the first phase to the second phase based on the first indication and the second indication.

    RECOGNIZING TRANSISTOR-TRANSISTOR LOGIC LEVELS (TTL) AT AN INPUT CIRCUIT WITH INCREASED IMMUNITY TO STATIC CURRENT DRAW
    4.
    发明申请
    RECOGNIZING TRANSISTOR-TRANSISTOR LOGIC LEVELS (TTL) AT AN INPUT CIRCUIT WITH INCREASED IMMUNITY TO STATIC CURRENT DRAW 审中-公开

    公开(公告)号：WO2021263277A1

    公开(公告)日：2021-12-30

    申请号：PCT/US2021/070761

    申请日：2021-06-23

    申请人： MICROCHIP TECHNOLOGY INCORPORATED

    发明人： DEVULAPALLI, Sridhar ,  RUSSELL, Daniel J. ,  CHEREK, Brian ,  KLEIN, Michael

    IPC分类号： H03K19/0185 ,  H03K19/00 ,  H03K19/0013 ,  H03K19/018521 ,  H03K3/037

    摘要： An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low. A third inverter may be maintained utilizing an input signal voltage to detect a falling edge of the input signal and turn ON power supply to the first inverter at least partially responsive thereto.

    전류 모드 로직 회로
    5.
    发明申请
    전류 모드 로직 회로 审中-公开

    公开(公告)号：WO2021172712A1

    公开(公告)日：2021-09-02

    申请号：PCT/KR2020/017832

    申请日：2020-12-09

    申请人： 한양대학교 산학협력단

    发明人： 한재덕

    IPC分类号： H03K19/094 ,  H03K19/00

    摘要： 일 실시예에 따른 전류 모드 로직 회로는 입력 전압과 연결되는 제1트랜지스터, 상기 제1트랜지스터와 병렬로 연결되는 제2 트랜지스터 및 상기 제1트랜지스터 및 제2트랜지스터와 연결되며, 상기 입력 전원에 의해 시간에 따라 적분된 출력 전압을 상기 적분과 반대되는 방향으로 적분을 하여 리셋 동작을 구현하는 전압 샘플링 회로를 포함할 수 있다.

    定電圧生成回路
    6.
    发明申请
    定電圧生成回路 审中-公开

    公开(公告)号：WO2021172001A1

    公开(公告)日：2021-09-02

    申请号：PCT/JP2021/004749

    申请日：2021-02-09

    申请人： ローム株式会社

    发明人： 安坂　信

    IPC分类号： G05F3/24 ,  H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K19/0944

    摘要： 出力電圧精度の高い定電圧生成回路を提供する。　定電圧生成回路（１）は、ＥＤ型基準電圧源を形成するデプレッション型の第１トランジスタ（Ｍ１）及びエンハンスメント型の第２トランジスタ（Ｍ２）と、前記第１トランジスタ（Ｍ１）のゲートとソースとの間に接続された抵抗（Ｒ１）を有する。例えば、前記第１トランジスタ（Ｍ１）及び前記第２トランジスタ（Ｍ２）は、ＮＭＯＳＦＥＴである。また、例えば、前記第１トランジスタ（Ｍ１）のドレインは、入力電圧（ＶＩＮ）の印加端に接続されており、前記第２トランジスタ（Ｍ２）のソースは、基準電位端に接続されており、前記第１トランジスタ（Ｍ１）及び前記第２トランジスタ（Ｍ２）それぞれのゲート及び前記第２トランジスタ（Ｍ２）のドレインは、定電圧（ＶＲＥＦ）の出力端に接続されている。

    TIMING EVENT DETECTOR, MICROELECTRONIC CIRCUIT, AND METHOD FOR DETECTING TIMING EVENTS
    7.
    发明申请
    TIMING EVENT DETECTOR, MICROELECTRONIC CIRCUIT, AND METHOD FOR DETECTING TIMING EVENTS 审中-公开

    公开(公告)号：WO2021165565A1

    公开(公告)日：2021-08-26

    申请号：PCT/FI2020/050108

    申请日：2020-02-20

    申请人： MINIMA PROCESSOR OY

    发明人： TURNQUIST, Matthew ,  KOSKINEN, Lauri

    IPC分类号： H03K3/037 ,  H03K19/003 ,  H03K19/00 ,  G06F11/07 ,  H03K5/1534 ,  H03K19/096 ,  G01R31/30 ,  G01R31/317 ,  G06F1/3296 ,  G06F11/30

    摘要： In a microelectronic circuit, a digital value (D) is temporarily stored in a register circuit (101). In relation to an allowable time limit defined by a triggering signal (CKP), there is stored a corresponding momentary value of said digital value (D) in differential form that comprises said momentary value (A) and its complement value (B). During a timing event detection window, any of said stored momentary value (A) or its stored complement value (B) may be toggled, however so that the stored momentary value (A) is only toggled in response to observing the digital value (D) change in one direction and the stored complement value (B) is only toggled in response to observing the digital value (D) change in the opposite direction. The stored momentary value (A) is compared to its stored complement value (B), and a timing event observation signal (TEO) is output (105) in response to said comparing showing that said stored momentary value (A) and its stored complement value (B) have become equal.

    CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES
    9.
    发明申请
    CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES 审中-公开

    公开(公告)号：WO2021133671A1

    公开(公告)日：2021-07-01

    申请号：PCT/US2020/066001

    申请日：2020-12-18

    申请人： INVENSAS BONDING TECHNOLOGIES, INC.

    发明人： DELACRUZ, Javier A. ,  HABA, Belgacem ,  KO, Jung

    IPC分类号： H01L25/065 ,  H03K19/00 ,  H03K3/037 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  G01R31/275 ,  G01R31/2856 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0657

    摘要： A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.