公开(公告)号：WO2009156873A1

公开(公告)日：2009-12-30

申请号：PCT/IB2009/051703

申请日：2009-04-26

Applicant: SANDISK IL LTD. ,  MURIN, Mark ,  SHARON, Eran

Inventor： MURIN, Mark ,  SHARON, Eran

IPC: G11C16/28 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G11C16/28 ,  G11C16/349 ,  G11C16/3495

Abstract: In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells.

Abstract translation: 在包括组织在多个位线和多个字线中的单元的非易失性存储器中，用户数据存储在两条字线中的每一个的相应部分中。 控制信息被存储在与位线之一和两条字线中的一条相同的单元中。 将位线和另一个字线共同的单元格用作参考单元。 询问包括多个主单元和多个备用单元的闪存，以确定哪些备用单元已被用于替换相应的主单元。 至少一些其他备用单元被用作参考单元。

公开(公告)号：WO2008056351A1

公开(公告)日：2008-05-15

申请号：PCT/IL2007/001344

申请日：2007-11-04

Applicant: SANDISK IL LTD. ,  SHLICK, Mark ,  MURIN, Mark

Inventor： SHLICK, Mark ,  MURIN, Mark

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C2211/5643

Abstract: When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the volatile memory to values above a verify voltage. While those threshold voltages remain substantially at those levels, the device raises the threshold voltages of other cells of the volatile memory to values below the verify voltage. In the end, every cell stores one or more bits from each plurality of bits. Preferably, all the cells share a common wordline. A data storage device operates similarly with respect to storing pluralities of bits generated by an application running on the system.

Abstract translation: 当存储器装置从主机接收两个或多个多个比特以存储在非易失性存储器中时，该装置首先将该比特存储在易失性存储器中。 然后，在将位存储在非易失性存储器中时，该器件将易失性存储器的一些单元的阈值电压提高到高于验证电压的值。 当这些阈值电压基本保持在这些电平时，器件将易失性存储器的其他单元的阈值电压升高到低于验证电压的值。 最后，每个单元存储来自每个位的一个或多个位。 优选地，所有细胞共享公共字线。 数据存储设备的操作类似地存储由在系统上运行的应用程序生成的多个位。

公开(公告)号：WO2008004216A2

公开(公告)日：2008-01-10

申请号：PCT/IL2007/000814

申请日：2007-07-01

Applicant: SanDisk IL Ltd. ,  MURIN, Mark

Inventor： MURIN, Mark

IPC: G11C11/34

CPC classification number: G11C8/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A multi-bit-per-cell flash memory device supports a command such that each invocation of the command by the device's host changes respective values of one or more types of reference voltage (e.g., all read reference voltages and/or all program verify reference voltages) of the device to respective new values.

Abstract translation: 多单元闪存设备支持命令，使得设备主机对命令的每次调用改变一种或多种类型的参考电压的相应值（例如，所有读取的参考电压和/或所有程序验证参考 电压）到相应的新值。

公开(公告)号：WO2006048861A3

公开(公告)日：2008-01-10

申请号：PCT/IL2005001116

申请日：2005-10-26

Applicant: MILSYS LTD ,  MURIN MARK

Inventor： MURIN MARK

IPC: G06F12/00

CPC classification number: G11C11/5628

Abstract: To store N bits of M=2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

Abstract translation: 为了存储M = 2个逻辑页的N位，这些位被交织，并且交织位被编程到[N / M]个存储单元，每个单元M位。 优选地，交织将来自每个逻辑页的相同数量的比特放入[N / M]个小区的每个比特页。 当从单元读取这些位时，这些位被解交织。 交织可以是确定性的或随机的，并且可以由软件或专用硬件实现。

公开(公告)号：WO2007029259A3

公开(公告)日：2007-11-15

申请号：PCT/IL2006001049

申请日：2006-09-07

Applicant: SANDISK IL LTD ,  LASSER MENACHEM ,  MURIN MARK ,  EYAL ARIK

Inventor： LASSER MENACHEM ,  MURIN MARK ,  EYAL ARIK

IPC: G06F12/00

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641

Abstract: A flash memory storage system (10) includes a memory array (12) containing a plurality of memory cells (14) and a controller (16) for controlling the flash memory array (12). The controller (16) dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells (14) to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells (14).

Abstract translation: 闪速存储器存储系统（10）包括包含多个存储器单元（14）的存储器阵列（12）和用于控制闪存阵列（12）的控制器（16）。 控制器（16）专用于第一组存储器单元以每个单元的第一位数和第二单独的存储单元组（14）以每单元的第二位数来操作。 提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元（14）。

公开(公告)号：WO2007083303A3

公开(公告)日：2007-07-26

申请号：PCT/IL2007/000061

申请日：2007-01-17

Applicant: SANDISK IL LTD. ,  MURIN, Mark

Inventor： MURIN, Mark

IPC: H03M13/00

Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

公开(公告)号：WO2007052259A2

公开(公告)日：2007-05-10

申请号：PCT/IL2006/001247

申请日：2006-10-30

Applicant: MSYSTEMS LTD. ,  MURIN, Mark ,  LASSER, Menahem ,  AVRAHAM, Meir

Inventor： MURIN, Mark ,  LASSER, Menahem ,  AVRAHAM, Meir

IPC: H01L21/00

CPC classification number: G11C29/16 ,  G11C11/5621 ,  G11C16/04 ,  G11C2029/0401

Abstract: Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.

Abstract translation: 公开了用于测试闪存芯片的方法，系统和设备。 根据一些实施例，在器件制造的后晶片分类阶段期间，多个闪存器件（其中每个闪存器件包括闪存控制器管芯和与公共壳体相关联的至少一个闪存管芯）经受测试过程 例如，批量测试过程或批量测试过程。 在测试期间，位于相应的闪存控制器芯片上的相应的闪存控制器执行至少一个测试程序来测试相应闪存设备的一个或多个相应的闪存存储器管芯。 公开了一种包括至少100个闪存器件和质量检测板的测试系统。 此外，公开了闪存控制器用于测试一个或多个闪速存储器管芯的闪存器件。 示例性测试包括但不限于坏块测试。

公开(公告)号：WO2007043042A2

公开(公告)日：2007-04-19

申请号：PCT/IL2006/001159

申请日：2006-10-04

Applicant: RAMOT AT TEL-AVIV UNIVERSITY LTD. ,  LITSYN, Simon ,  ALROD, Idan ,  SHARON, Eran ,  MURIN, Mark ,  LASSER, Menachem

Inventor： LITSYN, Simon ,  ALROD, Idan ,  SHARON, Eran ,  MURIN, Mark ,  LASSER, Menachem

IPC: G06F19/00

CPC classification number: G06F11/1072

Abstract: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract translation: 多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个 逻辑页面。 当从存储器读取页面时，读取的数据位使用读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：WO2007052259A3

公开(公告)日：2009-04-16

申请号：PCT/IL2006001247

申请日：2006-10-30

Applicant: SANDISK IL LTD ,  MURIN MARK ,  LASSER MENAHEM ,  AVRAHAM MEIR

Inventor： MURIN MARK ,  LASSER MENAHEM ,  AVRAHAM MEIR

IPC: G11C7/00

CPC classification number: G11C29/16 ,  G11C11/5621 ,  G11C16/04 ,  G11C2029/0401

Abstract: Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.

Abstract translation: 公开了用于测试闪存芯片的方法，系统和设备。 根据一些实施例，在器件制造的后晶片分类阶段期间，多个闪存器件（其中每个闪存器件包括闪存控制器管芯和与公共壳体相关联的至少一个闪存管芯）经受测试过程 例如，批量测试过程或批量测试过程。 在测试期间，位于相应的闪存控制器芯片上的相应的闪存控制器执行至少一个测试程序来测试相应闪存设备的一个或多个相应的闪存存储器管芯。 公开了一种包括至少100个闪存器件和质量检测板的测试系统。 此外，公开了闪存控制器用于测试一个或多个闪速存储器管芯的闪存器件。 示例性测试包括但不限于坏块测试。

公开(公告)号：WO2007054929A3

公开(公告)日：2009-04-09

申请号：PCT/IL2006001281

申请日：2006-11-06

Applicant: SANDISK IL LTD ,  MURIN MARK ,  SHLIK MARK

Inventor： MURIN MARK ,  SHLIK MARK

IPC: G06F12/00

CPC classification number: G11C16/26 ,  G06F12/0893 ,  G06F2212/2022

Abstract: A flash memory device (10) includes an array of memory cells (12) for storing data pages, at least one buffer (16) (e g a memory buffer and a cache buffer) for transferring the data pages to and from the array of memory cells and a host, and an output pin A logic mechanism (22) is operative to select, from among a plurality of conditions related to an operation on the array of memory cells (12), a condition that dnves a signal being output on the output pin A data page transfer by the host is contingent on the signal being output on the output pin.

Abstract translation: 闪速存储器件（10）包括用于存储数据页的存储器单元阵列（12），至少一个缓冲器（16）（例如存储器缓冲器和高速缓冲存储器），用于将数据页传送到存储器单元阵列 和主机，以及输出引脚A逻辑机构（22），用于从与存储器单元（12）阵列上的操作有关的多个条件中选择一个条件，该输出引脚输出输出的信号 引脚主机的数据页传输取决于输出引脚上输出的信号。