公开(公告)号：WO2020005592A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/037366

申请日：2019-06-14

Applicant: RAMBUS INC.

Inventor： WANG, Nanyan

IPC: G05B1/02 ,  H04L25/03 ,  H04L25/06

Abstract: A decision-feedback equalizer (DFE) samples an input signal with respect to a gamut of p reference- voltage levels to place the symbol represented by the input signal within a voltage region. The DFE derives a set of tentative decisions for the voltage region, the set excluding at least one of the possible values for the symbol under consideration. A feedback stage then selects a final decision from among the tentative decisions.

公开(公告)号：WO2018080783A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/055908

申请日：2017-10-10

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  LINSTADT, John, Eric ,  WRIGHT, Kenneth, L.

IPC: G06F11/10 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4093

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Abstract translation: 存储器模块包括服务于较大量的相对较慢且对磨损敏感的非易失性存储器的相对快速和持久的动态随机存取存储器（DRAM）的缓存。 本地控制器管理DRAM高速缓存和非易失性存储器之间的通信，以适应不同的访问粒度，减少必需的内存事务数量，并最大限度地减少非易失性内存组件外部的数据流。

公开(公告)号：WO2017192759A1

公开(公告)日：2017-11-09

申请号：PCT/US2017/030902

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  LINSTADT, John, Eric ,  HAUKNESS, Brent, Steven ,  WRIGHT, Kenneth, L. ,  VOGELSANG, Thomas

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4096

CPC classification number: G11C11/403 ,  G06F12/06 ,  G11C5/025 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/18 ,  G11C8/08 ,  G11C11/40618 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

Abstract translation: 存储器组件包括第一存储体。 第一存储体具有多个具有存储元件子行的子阵列。 存储器组件包括耦合到第一存储体的写入驱动器，用于执行子阵列的整个子行的写入操作。 要执行写入操作，写入驱动程序需要将一连串写入数据加载到内存条。 存储体然后可以激活与整个子行的多个存储元件相关联的多个读出放大器，以将写入数据的突发加载到多个读出放大器。

公开(公告)号：WO2017019495A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/043534

申请日：2016-07-22

Applicant: RAMBUS INC.

Inventor： GIOVANNINI, Thomas, J. ,  ABHYANKAR, Abhijit

IPC: H03H7/30

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

Abstract translation: 第一序列的数据比特在第一比特时间间隔序列期间被移入信号接收机的存储元件，并且存储器访问命令指示在第二序列期间在信号接收器内接收第二数据比特序列 的位时间间隔。 取决于在第一和第二比特时间间隔之间是否会发生一个或多个比特时间间隔，移位寄存器存储元件的内容被有条件地用预定的种子比特组重写。 至少部分地基于移位寄存器存储元件的内容生成的均衡信号用于调整代表第二数据位序列的一个或多个位的各个信号电平。

公开(公告)号：WO2016145328A3

公开(公告)日：2016-11-03

申请号：PCT/US2016022046

申请日：2016-03-11

Applicant: RAMBUS INC

Inventor： WARE FREDERICK ,  TSERN ELY ,  LINSTADT JOHN

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G11C5/063 ,  G11C5/04

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

Abstract translation: 公开了存储器控制器，设备，模块，系统和相关联的方法。 在一个实施例中，存储器模块包括用于经由总线耦合到存储器控制器的引脚接口。 该模块包括至少两个非易失性存储器件，以及设置在引脚接口和至少两个非易失性存储器件之间的缓冲器。 缓冲器从存储器控制器接收与DRAM存储器模块访问命令交错的非易失性存储器访问命令。

公开(公告)号：WO2016164242A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/025174

申请日：2016-03-31

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  ENDSLEY, Jay ,  GUIDASH, Michael ,  SMITH, Craig, M.

IPC: H04N5/3745 ,  H04N5/353

CPC classification number: H04N5/378 ,  H01L27/14634 ,  H04N5/3532 ,  H04N5/3535 ,  H04N5/35572 ,  H04N5/35581 ,  H04N5/357 ,  H04N5/369

Abstract: Multiple image data subframes corresponding to respective portions of an exposure interval are generated within a sensor device of an image system. Depending on whether the exposure interval exceeds one or more exposure time thresholds, data representative multiple image data subframes are output from the image sensor device in one of at least two formats, including a first format in which each of the subframes of image data is output in its entirety, and a second format in which a logical combination of at least two of the subframes of image data is output instead of the at least two of the subframes of image data such that the total volume of image data output from the image sensor device is reduced relative to the first format.

Abstract translation: 在图像系统的传感器装置内产生与曝光间隔的各个部分对应的多个图像数据子帧。 根据曝光间隔是否超过一个或多个曝光时间阈值，代表多个图像数据子帧的数据以至少两种格式之一从图像传感器装置输出，包括其中输出图像数据的每个子帧的第一格式 以及第二格式，其中输出图像数据的至少两个子帧的逻辑组合，而不是图像数据的至少两个子帧，使得从图像传感器输出的图像数据的总体积 设备相对于第一格式减少。

公开(公告)号：WO2016099846A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/063009

申请日：2015-11-30

Applicant: RAMBUS INC.

Inventor： WANG, Nanyan

IPC: H04B1/00

CPC classification number: H04L25/066 ,  H04L5/0048 ,  H04L25/4917 ,  H04L27/0002

Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

Abstract translation: 在PAM-N接收机中，采样器参考电平，DC偏移和AFE增益可以共同地适于实现用于PAM-N信号的符号决定的最佳或接近最佳边界。 对于参考电平适配，评估两个连续数据样本之间的汉明距离及其中间边缘样本。 相应地调整符号决策的参考电平，使得在数据转换时，边缘样本平均具有与其相邻数据样本相等的汉明距离。 可以补偿DC偏移，以确保参考电平适配的可检测数据转换。 AFE增益可以与采样器参考电平联合调整，使得参考电平和预定目标电压之间的差最小化。

公开(公告)号：WO2016081192A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/058956

申请日：2015-11-04

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  HARRIS, James, E.

IPC: G06F12/00

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

Abstract translation: 具有多个存储器件的存储器模块包括管理存储器控制器和存储器件之间的通信的缓冲器系统。 每个存储器件支持访问模式和低功耗模式，后者用于为不立即需要的设备节省电力。 该模块使用芯片选择解码器提供细粒度的功率管理，芯片选择解码器将来自存储器控制器的芯片选择信号解码为确定哪些存储器件是哪种模式的功率状态信号。 因此，根据需要，设备可以以相对较小的数量从低功率模式中脱离，以限制功耗。

公开(公告)号：WO2015183693A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/032006

申请日：2015-05-21

Applicant: RAMBUS, INC.

Inventor： VOGELSANG, Thomas ,  SMITH, Craig, M.

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/35581 ,  G06T7/248 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/2351 ,  H04N5/343 ,  H04N5/347 ,  H04N5/37457 ,  H04N5/378 ,  H04N9/045

Abstract: In an integrated-circuit image sensor having a pixel array, a first subframe readout policy is selected from among a plurality of subframe readout policies, each of the subframe readout policies specifying a first number of subframes of image data to be readout from the pixel array for each output image frame and respective exposure durations for each of the first number of subframes of image data, wherein a shortest one of the exposure durations is uniform for each of the subframe readout policies. Each of the first number of subframes of image data is read out from the pixel array following the respective exposure durations thereof while applying a respective analog readout gain. The analog readout gain applied during readout of at least a first subframe of the first number of subframes is scaled according to a ratio of the shortest one of the exposure durations to the exposure duration of the first subframe.

Abstract translation: 在具有像素阵列的集成电路图像传感器中，从多个子帧读出策略中选择第一子帧读出策略，每个子帧读出策略指定要从像素阵列读出的图像数据的第一数量子帧 对于每个输出图像帧和针对图像数据的第一数量子帧中的每一个的相应曝光持续时间，其中每个子帧读出策略的最短的一个曝光持续时间是均匀的。 在施加相应的模拟读出增益的同时，在其各自的曝光持续时间之后，从像素阵列中读出第一数量的图像数据的子帧。 在第一子帧的至少第一子帧的读出期间应用的模拟读出增益根据第一子帧的曝光持续时间中的最短一个的比率来缩放。

公开(公告)号：WO2015038867A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/055345

申请日：2014-09-12

Applicant: RAMBUS INC.

Inventor： NAVID, Reza

IPC: H03L7/081

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/083 ,  H03L7/24 ,  H04B1/22 ,  H04B1/7085

Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase- adjusted version of the clocking signal. The output of the edge sampler is used as a phase- error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

Abstract translation: 源同步时钟信号由由时钟信号的相位调整版本触发的边沿采样器采样。 边缘采样器的输出被用作滤波反馈回路的相位误差指示器，对准相位调整的时钟信号，平均地将接收到的源同步时钟信号和相位调整版本之间的差最小化 时钟信号减去采样器的建立时间。 这形成延迟锁定环路配置。 用于产生对准的相位调整时钟信号的相位调整信息然后产生用于对源同步数据信号进行采样的接收机时钟信号。