公开(公告)号：WO2015166500A1

公开(公告)日：2015-11-05

申请号：PCT/IL2015/050452

申请日：2015-04-30

Applicant: BAR-ILAN UNIVERSITY ,  B.G. NEGEV TECHNOLOGIES & APPLICATIONS LTD., AT BEN-GURION UNIVERSITY

Inventor： GITERMAN, Robert ,  TEMAN, Adam ,  MEINERZHAGEN, Pascal ,  BURG, Andreas ,  FISH, Alexander

IPC: G11C7/00

CPC classification number: G11C7/10 ,  G11C5/025 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

Abstract translation: 增益单元包括写位线输入，读位线输出，写触发输入和读触发输入。 增益单元还包括写入晶体管，保持元件和读取晶体管。 每个晶体管包括相应的第一扩散连接，栅极连接和第二扩散连接。 写晶体管第一扩散连接连接到写位线输入，写晶体管栅连接连接到写触发输入。 读取晶体管第一扩散连接连接到读位线输出，第二扩散连接连接到读触发输入。 在数据保持期间，保持元件在写晶体管和读晶体管之间缓冲。 保持元件还根据读取的晶体管栅极连接处的保持的数据电平将写入晶体管扩散连接与恒定电压连接或断开。

公开(公告)号：WO2012102183A1

公开(公告)日：2012-08-02

申请号：PCT/JP2012/051137

申请日：2012-01-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  YAMAZAKI, Shunpei ,  GODO, Hiromichi

Inventor： YAMAZAKI, Shunpei ,  GODO, Hiromichi

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/108 ,  G11C11/403 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/1037 ,  H01L29/22 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7869

Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

Abstract translation: 需要以几十毫秒的间隔刷新常规DRAM以保存数据，这导致大的功耗。 此外，其中的晶体管经常被打开和关闭; 因此，晶体管的劣化也是一个问题。 随着存储容量的增加和晶体管小型化的发展，这些问题变得越来越重要。 提供了一种晶体管，其包括氧化物半导体并且具有包括用于栅电极的沟槽和用于元件隔离的沟槽的沟槽结构。 即使当源电极和漏电极之间的距离减小时，通过适当地设置栅电极的沟槽的深度，可以抑制短沟道效应的发生。

公开(公告)号：WO2010080923A2

公开(公告)日：2010-07-15

申请号：PCT/US2010020387

申请日：2010-01-07

Applicant: CALIFORNIA INST OF TECHN ,  MOORE CHRISTOPHER D ,  KELLER SEAN J ,  MARTIN ALAIN J

Inventor： MOORE CHRISTOPHER D ,  KELLER SEAN J ,  MARTIN ALAIN J

IPC: G11C7/00 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C5/005 ,  G11C7/12 ,  G11C11/403 ,  G11C11/405 ,  G11C11/412

Abstract: A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by pre-charging the control section to a virtual drain voltage.

Abstract translation: 随机存取存储器（RAM）单元提供耦合到存储部分的控制部分和存储部分。 存储部分包括互补金属氧化物半导体（CMOS）晶体管，并且通过将控制部分预充电到虚拟漏极电压来读取存储部分。

公开(公告)号：WO1995033265A1

公开(公告)日：1995-12-07

申请号：PCT/US1995006771

申请日：1995-05-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MEHALEL, Moty

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C11/403 ,  G11C11/412 ,  G11C15/043

Abstract: A four-transistor memory cell having a cross coupled transistors (Q10, Q11) and a pair of pass gates (Q12, Q13) is disclosed. The four-transistor memory cell is refreshed by charge transfer between the bit lines (BL, BL#) and the internal node (90, 92) during bit line precharge.

Abstract translation: 公开了具有交叉耦合晶体管（Q10，Q11）和一对通孔（Q12，Q13）的四晶体管存储单元。 在位线预充电期间，四晶体管存储单元被位线（BL，BL＃）和内部节点（90,92）之间的电荷转移刷新。

公开(公告)号：WO2016176807A1

公开(公告)日：2016-11-10

申请号：PCT/CN2015/078224

申请日：2015-05-04

Applicant: 华为技术有限公司

Inventor： 肖世海 ,  黄永兵 ,  何睿

IPC: G11C11/406

CPC classification number: G11C29/783 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091

Abstract: 一种DRAM刷新方法、装置和系统，通过在刷新指令中指定一个刷新块block中需要刷新的区域，从而实现对DRAM存储整列的指定位置进行刷新，该方法包括：DRAM刷新装置接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息（S902），所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；所述DRAM刷新装置根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址（S904）；所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址对应的位置（S906）。从而缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加灵活，保证数据完整性的前提下，节省了系统资源的消耗。

公开(公告)号：WO2014171500A1

公开(公告)日：2014-10-23

申请号：PCT/JP2014/060887

申请日：2014-04-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： IKEDA, Takayuki

IPC: G11C11/405 ,  G11C11/4074 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786

CPC classification number: H03K19/0013 ,  G11C11/403 ,  H03K19/1776

Abstract: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is changed from a first potential into a second potential lower than the first potential, the logic element changes the potential of a first terminal of the first transistor from a third potential lower than the second potential into the first potential after the logic element changes the potential of the first terminal of the first transistor from the second potential into the third potential. The semiconductor element has a function of making a second terminal of the first transistor floating. The first transistor includes a channel formation region in an oxide semiconductor film.

Abstract translation: 提供了一种低功率存储设备。 存储装置包括第一晶体管，第二晶体管，逻辑元件和半导体元件。 第二晶体管控制向第一晶体管的栅极提供第一信号。 当要输入的第二信号的电位从第一电位变为低于第一电位的第二电位时，逻辑元件将第一晶体管的第一端子的电位从低于第二电位的第三电位变为 逻辑元件将第一晶体管的第一端子的电位从第二电位变为第三电位后的第一电势。 半导体元件具有使第一晶体管的第二端子浮置的功能。 第一晶体管包括氧化物半导体膜中的沟道形成区。

公开(公告)号：WO2011140044A3

公开(公告)日：2012-02-09

申请号：PCT/US2011034937

申请日：2011-05-03

Applicant: MICRON TECHNOLOGY INC

Inventor： CARMAN ERIC

IPC: G11C11/406 ,  G11C11/401

CPC classification number: G11C7/00 ,  G11C11/403 ,  G11C11/406 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array.

Abstract translation: 公开了用于刷新半导体存储器件的技术。 在一个特定示例性实施例中，可以实现这些技术，因为用于刷新半导体存储器件的方法可以包括将多个电压电位施加到存储器单元阵列中的存储器单元。 将多个电压电位施加到存储器单元可以包括经由阵列的相应源极线向存储器单元的第一区域施加第一电压电位。 将多个电压电位施加到存储器单元还可以包括经由相应的本地位线和阵列的相应选择晶体管将第二电压电位施加到存储器单元的第二区域。 将多个电压电位施加到存储器单元还可以包括将第三电压电位施加到阵列的相应字线，其中字线可以与存储器单元的体区间隔开并且电容地与电容器电连接 浮置并设置在第一区域和第二区域之间。 将多个电压电位施加到存储器单元还可以包括经由阵列的相应载体注入线将第四电压电位施加到存储器单元的第三区域。

公开(公告)号：WO2011099389A1

公开(公告)日：2011-08-18

申请号：PCT/JP2011/051845

申请日：2011-01-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  INOUE, Hiroki ,  KATO, Kiyoshi ,  MATSUZAKI, Takanori ,  NAGATSUKA, Shuhei

Inventor： INOUE, Hiroki ,  KATO, Kiyoshi ,  MATSUZAKI, Takanori ,  NAGATSUKA, Shuhei

IPC: H01L21/8242 ,  G11C11/401 ,  G11C11/405 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/24 ,  G11C11/403 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.

Abstract translation: 目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。 半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。 因此，可以充分降低半导体器件的功耗。