公开(公告)号：WO1994016461A1

公开(公告)日：1994-07-21

申请号：PCT/US1993012632

申请日：1993-12-27

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  CHANG, Kuang-Yeh ,  WEI, Yi-Hen

IPC: H01L27/02

CPC classification number: H01L21/76218 ,  H01L21/8249

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS devices are disclosed. According to the present invention, over-etching to the substrate (2) on the deposited polysilicon emitter (25) is prevented by providing additional oxide (22) beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an endpoint during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT (self-aligned transistor) masking and oxidation steps.

Abstract translation: 公开了一种制造BiCMOS器件的方法，以及所得到的BiCMOS器件。 根据本发明，通过在多晶硅层下方提供附加氧化物（22）作为蚀刻停止来防止沉积的多晶硅发射极（25）上的衬底（2）的过度蚀刻。 尽管包含氧化物以在发射体图案化期间限定端点，但是通过避免附加的SAT（自对准晶体管）掩模和氧化步骤来降低制造复杂性。

公开(公告)号：WO1994015261A1

公开(公告)日：1994-07-07

申请号：PCT/US1993011339

申请日：1993-11-22

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  LEROUX, Pierre

IPC: G03F07/22

CPC classification number: G03F1/34 ,  G03F1/28 ,  G03F7/2022 ,  G03F7/2024 ,  G03F7/70466

Abstract: Ultra-small equal-width lines and spaces are generated on an integrated circuit wafer using multiple exposures and phase-shifting at the wafer level. In particular, an integrated circuit wafer is coated with a layer of photoresist and then masked using a mask defining a pattern of multiple feature lines arranged at a regular line pitch. The layer of photoresist is then underexposed so as to partially bleach portions of the layer of the photoresist in accordance with the pattern. Next, the mask and the integrated circuit wafer are positionally translated relative to one another by a predetermined fraction of the line pitch, and the layer of photoresist is then again underexposed. Developing the photoresist layer creates a stepped profile. The layer of photoresist is then blanket exposed, the stepped profile causing exposure in the vicinity of steps to be retarded. The layer of photoresist is then developed, producing thin lines of photoresist separated by substantially equal spaces of no photoresist.

Abstract translation: 在集成电路晶片上使用多个曝光和晶片级的相移产生超小的等宽线和间隔。 特别地，集成电路晶片涂覆有一层光致抗蚀剂，然后使用限定以规则线间距布置的多个特征线的图案的掩模进行掩模。 然后光致抗蚀剂层曝光不足，以便根据图案部分地漂白光致抗蚀剂层的部分。 接下来，掩模和集成电路晶片相对于彼此以线间距的预定分数位置地平移，然后光致抗蚀剂层再次曝光不足。 显影光致抗蚀剂层产生阶梯轮廓。 然后，光致抗蚀剂层被橡皮布暴露，阶梯状轮廓导致在步骤附近的曝光被延迟。 然后显影光致抗蚀剂层，产生由基本上相等的没有光致抗蚀剂的空间分开的光致抗蚀剂层。

公开(公告)号：WO1994015220A1

公开(公告)日：1994-07-07

申请号：PCT/US1993012273

申请日：1993-12-16

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  GANAPOL, David, L. ,  MARCUSE, Arno, G.

IPC: G01R01/04

CPC classification number: G01R1/04

Abstract: Test jig apparatus for testing an integrated circuit chip that suppresses build-up and subsequent discharge of electrical charge on the test jig apparatus or on the chip. The test jig apparatus includes a base (33) of selected material having a top surface (34) of the same general shape and dimensions as the chip to be tested. Preferably, the entire top surface of the base is electrically grounded. The base has two or more side surfaces (37, 39) with side surface planes that are approximately perpendicular to a plane defining the top surface of the base. Each side surface accepts a side plate (47, 49, 51, 53), made of a selected material such as ULTIM, than can be attached to or removed from the base. The side plane material resists electrical charge buildup and subsequent discharge so that the chip being tested is not subjected to electrical discharge from this source. In another embodiment, the side plates are replaced by plates (67, 69) mounted on the top surface of the base.

Abstract translation: 用于测试集成电路芯片的测试夹具装置，其抑制在测试夹具装置或芯片上积累和随后的电荷放电。 测试夹具装置包括具有与待测芯片相同的大致形状和尺寸的顶表面（34）的所选材料的基部（33）。 优选地，基座的整个顶表面电接地。 底座具有两个或更多个侧表面（37,39），侧表面平面大致垂直于限定底座顶表面的平面。 每个侧面接受由诸如ULTIM的选定材料制成的侧板（47,49,51,53），比可以附接到基座或从底座移除的侧板（47,49,51,53）。 侧面材料抵抗电荷累积和随后的放电，使得被测试的芯片不会从该源放电。 在另一个实施例中，侧板被安装在基座顶面上的板（67,69）代替。

公开(公告)号：WO1994011840A1

公开(公告)日：1994-05-26

申请号：PCT/US1993011166

申请日：1993-11-17

Applicant: VLSI TECHNOLOGY, INC. ,  EDWARDS, Lawrence, Byron

Inventor： VLSI TECHNOLOGY, INC.

IPC: G06F15/60

CPC classification number: G06F17/5081

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processed in a sorted order. For each cell, width and spacing design rules are applied to first and second edges of the cell, which may result in movement of the cell and/or adjustment of the cell's width. An adjacent cell adjustment process conforms cells shared points with the adjusted cell. Once the compaction procedure is carried out in a positive x-direction, the coordinates are reversed and it is carried out again in a second pass. The compaction method is performed once for x-direction compaction and once for y-direction compaction. The compaction process is computationally efficient because each cell is linked by the database to its adjacent cells, virtually eliminating the need to search through cells not needed for each design rule check, and because movement of one cell's edges automatically adjusts adjacent cells via their shared edges. The wire minimization embodiment of the invention includes determining whether the second edges have been moved in the second pass, and if so applying the width rules to the first edges to minimize the length of wire represented by the width of the cell having the adjusted edges.

Abstract translation: 用于压缩半导体电路布局以满足规定的一组设计规则的计算机辅助设计方法和装置通过将指定的电路布局压裂成一组梯形开始，并将所得到的单元存储在识别每个单元的边界的数据库中，并且 相邻每个边界的单元格。 该方法另外包括用于最小化压实布局中的导线长度的步骤。 非空细胞被鉴定为特定材料，并且表示细胞之间的空白空间。 对于每个单元格边界，数据库还存储表示边界边缘端点的数据。 电路布局的相同层和相关层上的相邻单元共享数据库中的边。 当单元格边缘上的点被移动时，共享该点的每个相邻单元格的边缘也被移动。 要调整电路布局，布局中的单元格按排序顺序进行处理。 对于每个单元，宽度和间距设计规则被应用于单元的第一和第二边缘，这可能导致单元的移动和/或单元格宽度的调整。 相邻小区调整过程将小区共享点与调整小区一致。 一旦在正x方向上执行压实过程，则坐标反转，并且在第二遍中再次执行。 对于x方向压实执行一次压实方法，对于y方向压实执行一次。 压缩过程在计算上是有效的，因为每个单元由数据库连接到其相邻单元，实际上消除了对每个设计规则检查不需要的单元格进行搜索的需要，并且因为一个单元格边缘的移动通过它们的共享边缘自动调整相邻单元格 。 本发明的线最小化实施例包括确定在第二遍中是否已经移动了第二边缘，并且如果这样将宽度规则应用于第一边缘以最小化由具有调整边缘的单元的宽度表示的布线的长度。

公开(公告)号：WO1993020678A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002663

申请日：1993-03-16

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  CARICHNER, Karla, Y. ,  BUGARIN, John, V.

IPC: H05K13/00

CPC classification number: H05K13/0084 ,  H01L2221/68313

Abstract: A spacer tray is disclosed. This spacer tray finds use in handling or shipping semiconductor packages having surface projections which extend the height of the semiconductor package beyond normal semiconductor height parameters. The spacer tray is generally used in conjunction with a standard carrier tray which holds the semiconductor base (i.e., the semiconductor body and leads). The spacer tray comprises a tray body having at least one bore, the bore being sized to house the semiconductor surface projection(s) while excluding the semiconductor base. Methods of use are also given.

Abstract translation: 公开了间隔盘。 该间隔盘可用于处理或运输具有使半导体封装的高度超过正常半导体高度参数的表面突起的半导体封装。 隔离盘通常与保持半导体基座（即，半导体本体和引线）的标准载体托盘结合使用。 间隔托盘包括具有至少一个孔的托盘主体，该孔的尺寸适于容纳半导体表面突起，同时排除半导体基底。 还给出了使用方法。

公开(公告)号：WO1993013591A1

公开(公告)日：1993-07-08

申请号：PCT/US1992010992

申请日：1992-12-17

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  CLARK, Lawrence, Twilley

IPC: H03D03/24

CPC classification number: H03L7/089 ,  G11B20/10212

Abstract: A digital filter for a phase-locked loop operates to compare the bit values of the data represented by the incoming pulse stream (10) with patterns in that pulse stream known to produce bit shifting (either early or late). The bit shift caused by physical interaction of bits encoded on computer diskettes or the like always is predictable, in accordance with the pattern of previous bits, the current bit and the next bit. This information is processed by a logic circuit (18, 21) to predict which pulses in the incoming stream of data pulses are shifted. A signal is produced each time a predicted shifted pulse is determined; and this signal is utilized (in 21) in conjunction with the output of a phase difference counter (20) in the digital phase-locked loop to permit the phase of the controlled oscillator (14) to be adjusted at each unshifted bit in a normal manner, and compensated for adjustment in a modified manner as a result of the prediction of the shifted pulses.

公开(公告)号：WO1993010558A1

公开(公告)日：1993-05-27

申请号：PCT/US1992008260

申请日：1992-09-29

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  BOARDMAN, William, J. ,  LOH, Ying, Tsong ,  NOWAK, Edward, D. ,  WANG, Chung, Shu

IPC: H01L21/336

CPC classification number: H01L29/66606

Abstract: For a structure with an overlapping gate region, a first insulator layer (35) is placed on a substrate. A source/drain polysilicon layer (37) is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer (38) is placed on the source/drain polysilicon layer. A gap (39) is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount (40) of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions (42, 43) are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region (45) is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region (44). Source/drain regions (47, 48, 49, 50) are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler regions into the substrate.

公开(公告)号：WO1993009566A1

公开(公告)日：1993-05-13

申请号：PCT/US1992008265

申请日：1992-09-29

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  GABRIEL, Calvin, T.

IPC: H01L23/31

CPC classification number: H01L23/3192 ,  H01L23/3171 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S438/958 ,  H01L2924/00

Abstract: For passivation of an integrated circuit device, a film of silicon dioxide (32) is deposited over the integrated circuit device. A film of silicon nitride (33) is deposited over the film of silicon dioxide. The film of silicon nitride and the film of silicon dioxide are etched using a single passivation mask to expose the bond pads of the integrated circuit device. Spacer regions (35) of silicon nitride are placed over edges of the film of silicon dioxide exposed by the etching. The spacer regions may be placed by depositing a second film of silicon nitride (34) over the film of silicon nitride. This second film of silicon nitride covers the metal bond pads and the exposed edges of the film of silicon dioxide. An anisotropic etchback of the second film of silicon nitride is performed to expose the metal bond pads while leaving spacer regions which cover the edges of the film of silicon dioxide.

公开(公告)号：WO1993005514A1

公开(公告)日：1993-03-18

申请号：PCT/US1992007453

申请日：1992-09-03

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  BOARDMAN, William, J. ,  CHAN, David, P-Kwan ,  CHANG, Kuang-Yeh ,  GABRIEL, Calvin, T. ,  JAIN, Vivek ,  NARIANI, Subhash, R.

IPC: G11C17/16

CPC classification number: H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer (10); forming an anti-fuse layer (20) over the base layer; patterning the anti-fuse layer to form an anti-fuse island (24a, 24b); forming an insulating layer (26) over the anti-fuse island; forming a via hole (28a, 28b, 28c) through the insulating layer to the anti-fuse island; forming a conductive connection layer (32) over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact (30a, 30b, 30c) to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

Abstract translation: 一种制造抗熔丝结构的方法，其特征在于形成导电基层（10）的步骤。 在所述基底层上形成抗熔融层（20）; 图案化抗熔丝层以形成抗熔丝岛（24a，24b）; 在所述反熔丝岛上形成绝缘层（26）; 形成通过所述绝缘层到所述反熔丝岛的通孔（28a，28b，28c）; 在所述绝缘层上并在所述通孔内形成导电连接层（32）; 以及图案化所述导电连接层以形成到所述反熔丝岛的导电接触（30a，30b，30c）。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

公开(公告)号：WO1993000706A1

公开(公告)日：1993-01-07

申请号：PCT/US1992003584

申请日：1992-04-30

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  LONG, Jon, M.

IPC: H01L23/28

CPC classification number: H01L21/6835 ,  H01L21/4821 ,  H01L22/32 ,  H01L2924/0002 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00

Abstract: After a semiconductor die (20) is placed onto a leadframe (22) and electrically connected to the die (20), the die (20) and the ends of the leads (26) adjacent to the die (20) are encased in a packaged body (30). The exposed ends (26c, 26b) of the leads (26) are trimmed so that the leads (26) are of desired lengths for leadforming, or for connection to substrates or sockets. The ends of the leads (26) are enclosed in a protective body (60), so that when the package is tested and handled, the protective body (60) reduces indesirable bending of the leads (26). By trimming the leads (26) before forming the protective body (60), the leadframe (22) used need not be larger than those normally used.