公开(公告)号：WO2023288004A2

公开(公告)日：2023-01-19

申请号：PCT/US2022/037174

申请日：2022-07-14

Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA

Inventor： JACOB, Ajey Poovannummoottil ,  KAPADIA, Rehan Rashid

IPC: H01L21/02 ,  H01L21/762 ,  C30B19/00 ,  C30B19/12 ,  H01L21/02376 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02623 ,  H01L29/70

Abstract: A method for fabricating low defective non-planar bipolar heterostructure transistors includes a steps of providing a substrate that is coated with a first dielectric layer when the substrate is not composed of a dielectric material. A layer of a first semiconductor material is formed by template liquid phase (TLP) crystal growth wherein a second dielectric layer is disposed over the first semiconductor material. A trench is patterned into the second dielectric layer. An intermediate heterostructure is formed by epitaxially growing second semiconductor material in the trench to form a fin structure therein. Various power transistor structures can be formed from the intermediate heterostructure.

公开(公告)号：WO2022239948A1

公开(公告)日：2022-11-17

申请号：PCT/KR2022/003477

申请日：2022-03-11

Applicant: 주성엔지니어링(주)

Inventor： 허정 ,  김덕호 ,  김용현 ,  마창수 ,  박창균 ,  이용현 ,  황철주

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/34 ,  C23C16/455 ,  C23C16/0272 ,  C23C16/4554 ,  C23C16/45553 ,  C23C16/56 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02667

Abstract: 본 발명은 박막 형성 방법에 관한 것으로서, 보다 상세하게는 질화갈륨 박막을 형성하기 위한 박막 형성 방법에 관한 것이다. 본 발명의 실시 예에 따른 박막 형성 방법은, 챔버의 공정 공간에 기판을 반입하는 단계; 및 상기 기판 상에 질화갈륨 박막을 형성하는 단계;를 포함하고, 상기 질화갈륨 박막을 형성하는 단계는, 상기 기판 상에 갈륨을 함유하는 소스 가스를 공급하는 단계; 상기 기판 상에 질소를 함유하는 리액턴트 가스를 공급하는 단계; 및 상기 리액턴트 가스가 공급된 기판 상에 수소를 함유하는 후처리 가스를 활성화시켜 공급하는 단계;를 포함한다.

公开(公告)号：WO2021258293A1

公开(公告)日：2021-12-30

申请号：PCT/CN2020/097752

申请日：2020-06-23

Applicant: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

Inventor： WU, Peng-Yi

IPC: H01L29/06 ,  H01L29/778 ,  H01L21/335 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02647 ,  H01L29/0684 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7786

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first layer and a second layer. The first layer is disposed on and in contact with the substrate. The first layer includes AlX1Ga (1-X1) N, wherein 0.5≤X1

公开(公告)号：WO2021195595A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/024529

申请日：2021-03-26

Applicant: GOOGLE LLC

Inventor： DAVID, Aurelien Jean Francois

IPC: H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L33/08 ,  H01L33/12 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02647 ,  H01L33/0075 ,  H01L33/0093

Abstract: A method of forming an LED emitter includes: providing a Ill-nitride layer on a substrate (310), the Ill-nitride layer having a planar top surface; providing discrete lateral growth regions on the top surface; selectively epitaxially growing, on each discrete lateral growth region, a base region (1210) comprising an In(x)Ga(l-x)N material, each extending perpendicular to the top surface; providing surfaces of the In(x)Ga(l-x)N material on portions of the base regions (1210), the surfaces having a relaxed strain and being characterized by a base lattice constant within 0.1% of its bulk relaxed value; and epitaxially growing LED regions on the surfaces, the LED regions including light- emitting layers of In(y)Ga(l-y)N material that are pseudomorphic with the surfaces of the In(x)Ga(l-x)N material, and characterized by an active region (1240) lattice constant within 0.1% of the base lattice constant, wherein 0.05 0.3.

公开(公告)号：WO2021148813A1

公开(公告)日：2021-07-29

申请号：PCT/GB2021/050158

申请日：2021-01-22

Applicant: PORO TECHNOLOGIES LTD

Inventor： ALI, Muhammad ,  OLIVER, Rachel ,  ZHU, Tongtong

IPC: H01L33/12 ,  H01L33/16 ,  H01L33/32 ,  H01L33/00 ,  H01L21/02 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L33/0075

Abstract: A semiconductor structure comprises a layer of a first III-nitride material having a first lattice dimension; a non-porous layer of a second III-nitride material having a second lattice dimension different from the first lattice dimension; and a porous region of III-nitride material disposed between the layer of first III-nitride material and the non-porous layer of the second III-nitride material. An optoelectronic semiconductor device, an LED, and a method of manufacturing a semiconductor structure are also provided.

公开(公告)号：WO2021126445A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/060961

申请日：2020-11-18

Applicant: LUMILEDS LLC

Inventor： WILDESON, Isaac ,  LOPEZ, Toni ,  ARMITAGE, Robert ,  DEB, Parijat

IPC: H01L33/00 ,  H01L21/02 ,  H01L33/20 ,  H01L21/02403 ,  H01L21/02414 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/0254 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/22 ,  H01L33/32

Abstract: Light emitting diode (LED) devices comprise: a patterned substrate comprising a substrate body, a plurality of integral features protruding from the substrate body, and a base surface defined by spaces between the plurality of integral features; a selective layer comprising a dielectric material located on the surfaces of the integral features, wherein there is an absence of the selective layer on the base surface; and a III-nitride layer comprising a III-nitride material on the selective layer and the base surface.