公开(公告)号：WO2014150733A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024089

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  ZENG, Mao ,  HOFFMAN, Marc M.

IPC: H04B1/7093 ,  H04B1/7075 ,  H03H17/02

CPC classification number: H04L25/0212 ,  H04B1/70752 ,  H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。

公开(公告)号：WO03026147A3

公开(公告)日：2003-06-19

申请号：PCT/US0230001

申请日：2002-09-19

Applicant: QUALCOMM INC

Inventor： RAO SUBRAMANYA P ,  VENKATESAN SIVARAMA ,  GHO GWANG-HYUN ,  AGRAWAL AVNEESH ,  TERASAWA DAISUKE

IPC: H04B1/7073 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/7083 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38 ,  H04B1/707 ,  H04B7/26

CPC classification number: H04B1/7077 ,  H04B1/70735 ,  H04B1/70752 ,  H04B1/7083 ,  H04B1/709 ,  H04B1/7093 ,  H04B2201/70701 ,  H04B2201/70707

Abstract: Techniques for searching in asynchronous systems are disclosed. In one aspect, a plurality of codes, such as SSCs, are correlated with a received signal at a plurality of offsets to produce a code/slot energy corresponding to each code/slot boundary pair. Unique subsets of the code/slot energies are summed to produce code sequence energies, the maximum of which indicates a located code sequence and slot boundary. In another aspect, the correlation is performed by sub-correlating the received signal with a common sequence, and performing a Fast Hadamard Transform FHT on the results. In yet another aspect, one sub-correlator can be used to search a plurality of peaks simultaneously. Various other aspects of the invention are also presented. These aspects collectively have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

Abstract translation: 公开了在异步系统中搜索的技术。 在一个方面，诸如SSC的多个代码与多个偏移处的接收信号相关，以产生对应于每个代码/时隙边界对的代码/时隙能量。 代码/时隙能量的独特子集被相加以产生代码序列能量，其最大值表示定位的代码序列和时隙边界。 在另一方面，通过将接收到的信号与公共序列进行子相关并且对结果执行快速Hadamard变换FHT来执行相关性。 在另一方面，可以使用一个子相关器同时搜索多个峰值。 还提出了本发明的各种其它方面。 这些方面共同具有电路面积和搜索时间效率的优点，其转化为降低的成本，增加的待机时间，增加的采集速度，更高质量的信号传输，增加的数据吞吐量，降低的功率以及改善的整体系统容量。

公开(公告)号：WO02045288A2

公开(公告)日：2002-06-06

申请号：PCT/US2001/043619

申请日：2001-11-20

IPC: H04B1/707 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38

CPC classification number: H04B1/707 ,  H04B1/709 ,  H04B2001/70935

Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

Abstract translation: 接收器单元包括以特定采样率接收和存储数字化采样的第一缓冲器，以及从第一缓冲器检索数字化样本的段并且使用特定参数值集处理检索的段的数据处理器。 数据处理器基于具有比采样率高的（例如，或多次）的频率的处理时钟来操作。 可以通过从第一缓冲器检索和处理数字化样本的多个部分来处理接收信号的多个实例。 接收器单元通常还包括接收和处理发射信号以提供数字化样本的接收机以及为数据处理器分派任务的控制器。 数据处理器可以被设计为包括相关器，符号解调和组合器，第一累加器和第二缓冲器，或其组合。 相关器对所取回的数字化样本段进行解扩，以对应的解扩序列段进行解扩，以提供相关样本，由符号解调和组合器进一步处理，以提供处理后的符号。 第二缓冲器存储经处理的符号，并且可以被设计为提供经处理符号的解交织。

公开(公告)号：WO02033836A1

公开(公告)日：2002-04-25

申请号：PCT/US2000/028363

申请日：2000-10-13

IPC: H04B1/708 ,  H04B1/7093 ,  H04B1/10

CPC classification number: H04B1/7093 ,  H04B1/708

Abstract: The present invention is a match filter (10) architecture that is used in the Spread ALOHA Multiple Access (SAMA) receiver to facilitate the separation of individual user's data from the incoming SAMA sample "chip" stream. The filter outputs the convolution of the incoming signals with the matched filter impulse response at the same rate as the sampling of incoming chips, thus providing a means to detect more than one user within one match pattern interval. The filter operates completely synchronously with a high frequency filter clock, which is used to generate the sample clock. Incoming chip samples are loaded in the delay shift register (7) at the sample clock rate. The samples are shifted at the filter clock frequency. Each bit in the chip trickles down through serial adders (11), with one clock period of delay for each serial adder (11). At the final accumulator (23), the serial sum bits are collected for parallel presentation to output registers at the sampling frequency.

Abstract translation: 本发明是在扩频ALOHA多路访问（SAMA）接收机中使用的匹配滤波器（10）架构，以便于将各个用户的数据与进入的SAMA采样“芯片”流分离。 滤波器以与进入芯片的采样相同的速率输出输入信号与匹配滤波器脉冲响应的卷积，从而提供在一个匹配模式间隔内检测多于一个用户的装置。 滤波器与用于产生采样时钟的高频滤波器时钟完全同步运行。 以采样时钟速率将进入的芯片样本加载到延迟移位寄存器（7）中。 样本以滤波器时钟频率移位。 芯片中的每一位都通过串行加法器（11）进行下降，每个串行加法器（11）的延迟一个时钟周期。 在最终累加器（23）处，采集串行和位以便以采样频率并行显示给输出寄存器。

公开(公告)号：WO01095534A2

公开(公告)日：2001-12-13

申请号：PCT/US2001/017777

申请日：2001-06-01

IPC: G06E3/00 ,  H04B1/7093 ,  H04B1/7103 ,  H04J14/00 ,  H04J13/00 ,  H04B1/707

CPC classification number: G06E3/00 ,  H04B1/7093 ,  H04B1/7103 ,  H04J14/005

Abstract: A method and apparatus for enhancing the receiving and information identification functions of multiple access communications systems by employing one or more optical processors configured as a bank of 1-D correlators. The present invention is particularly useful in a DS/SS CDMA communications system, resulting in a multiuser CDMA system that approaches carrier to noise performance (C/N) as opposed to being limited by multiple access interference (MAI). The correlators are arranged in parallel to detect and/or demodulate the received signal, in conjunction with one or more complex algorithms to perform near-optimum multiuser detection, perform multipath combining and/or perform carrier Doppler compensation. An improved receiver in accordance with the present invention comprises means for receiving a plurality of signals transmitted through a communications channel; signal conversion means for converting the received signals into a form suitable for input to the multichannel correlator; a multichannel optical correlator for identifying the presence of particular waveforms and estimating the relative time delay or delays, carrier frequency offset from expected, RF amplitude and RF phase for each received spread spectrum waveform present in the received plurality of signals; a controller for determining and providing to the optical correlator the appropriate set of reference hypotheses; and one or more receiver algorithms depending on the exact receiver function to be performed.

Abstract translation: 一种用于通过使用被配置为1-D相关器组的一个或多个光学处理器来增强多址接入通信系统的接收和信息识别功能的方法和装置。 本发明在DS / SS CDMA通信系统中特别有用，从而产生了一种多用户CDMA系统，其处理载波噪声性能（C / N），而不是受到多址干扰（MAI）的限制。 结合一个或多个复杂算法执行近最佳多用户检测，执行多路径组合和/或执行载波多普勒补偿，相关器并行布置以检测和/或解调所接收的信号。 根据本发明的改进的接收机包括用于接收通过通信信道发送的多个信号的装置; 信号转换装置，用于将接收到的信号转换成适合于输入到多声道相关器的形式; 用于识别特定波形的存在并估计相对时间延迟或延迟，载波频率偏离与所接收的多个信号中存在的每个接收的扩频波形的预期的RF幅度和RF相位; 控制器，用于确定并向光学相关器提供适当的参考假设集合; 和一个或多个接收机算法，这取决于要执行的确切接收机功能。

公开(公告)号：WO0158041A2

公开(公告)日：2001-08-09

申请号：PCT/US0103380

申请日：2001-02-02

Applicant: INTERDIGITAL TECH CORP

Inventor： ZEIRA ARIELA ,  ZEIRA ELDAD ,  REZNIK ALEXANDER ,  TERRY STEPHEN E

IPC: H04B1/707 ,  H04B1/7073 ,  H04B1/7093 ,  H04B1/7103 ,  H04B1/7105 ,  H04B7/00 ,  H04J3/00 ,  H04J11/00 ,  H04J13/00 ,  H04J13/16 ,  H04Q7/38

CPC classification number: H04B1/7103 ,  H04B1/707 ,  H04B1/70735 ,  H04B1/7105 ,  H04B2001/70935 ,  H04B2201/70701 ,  H04B2201/70709 ,  H04J13/00 ,  H04J13/16

Abstract: A wireless time division duplex communication system using code division multiple access has a base station and user equipments. The system communicates using communication bursts. Each communication burst has a unique channelization code and a midamble code. Each midamble code is mapped to a set of at least one channelization code. For each communication burst to be transmitted in a time slot from the base station, the midamble code mapped to that burst's channelization code is determined. Communication bursts are generated and transmitted in the time slot. Each burst has the determined midamble code for its channelization code. The user equipment receives the bursts and determines each received midamble code. The user equipment determines the channelization codes of the transmitted communication bursts based on in part a result of the determining of each received midamble code.

Abstract translation: 使用码分多址的无线时分双工通信系统具有基站和用户设备。 系统使用通信突发进行通信。 每个通信突发具有唯一的信道化码和中间码。 每个中间码代码被映射到一组至少一个信道化码。 对于要在基站的时隙中发送的每个通信突发，确定映射到该突发的信道化码的中间码。 在时隙中生成和发送通信突发。 每个突发具有确定的其信道化码的中间码代码。 用户设备接收突发并确定每个接收到的中间码。 用户设备部分地基于确定每个接收到的中间码的结果来确定所发送的通信脉冲串的信道化码。

公开(公告)号：WO01030015A1

公开(公告)日：2001-04-26

申请号：PCT/US1999/024425

申请日：1999-10-18

IPC: G06F17/15 ,  H04B1/709 ,  H04B1/7093 ,  H04L7/00

CPC classification number: H04B1/7093 ,  G06F17/15 ,  H04B1/709

Abstract: An apparatus for receiving a data stream having a plurality of time domain spread spectrum messages in the same frequency channel. Each message is independent, spread spectrally with a unique code and the data stream contains a subset of all known codes. The apparatus finds a specific code and a constant phase shift between the incoming code and a reference code by serially moving the data stream through a shift register (40), subjecting all the shift register outputs to a single expected reference code and accumulating the result for each output using a plurality of accumulators (42). The code and phase shift is indicated by the largest magnitude of the accumulation, above a threshold, generated by circuit (48), corresponding to the shift register output for the correct phase shift betwen the incomming code and the reference. When an integration cycle terminates, the time shift delay increases by the length of the shift register (40). The process continues for all possible relative time shifts and all the reference codes.

Abstract translation: 一种在相同频道中接收具有多个时域扩频消息的数据流的装置。 每个消息是独立的，利用唯一的码进行频谱扩展，并且数据流包含所有已知代码的子集。 该装置通过串行地移动数据流通过移位寄存器（40），找到特定的代码和输入代码和参考代码之间的恒定相移，使所有的移位寄存器输出接受单个期望的参考代码，并将结果累加到 每个输出使用多个累加器（42）。 代码和相移通过由电路（48）产生的累加值的最大值（由阈值产生）表示，对应于移位寄存器输出，用于在输入代码和参考值之间进行正确的相移。 当积分周期终止时，时移延迟增加移位寄存器（40）的长度。 该过程将持续所有可能的相对时间和所有参考代码。

公开(公告)号：WO01029983A1

公开(公告)日：2001-04-26

申请号：PCT/US2000/003537

申请日：2000-02-11

IPC: H04B1/707 ,  H04B1/7093 ,  H04B1/7103 ,  H04B1/7105 ,  H04B1/7107 ,  H04B3/06 ,  H04B7/005

CPC classification number: H04B1/71075 ,  H04B1/7093 ,  H04B1/7103 ,  H04B1/71052

Abstract: A receiver that reduces impulse response interference using a model of the received signal similar to that used in block linear equalizers. Block linear equalizers comprise decorrelating receivers, zero-forcing receivers, minimum mean square error receivers and the like. The invention comprises an interference computation processor feedback loop (43) for correcting the output of a direct interference canceller (39). The m iterative process removes interferers from the output symbols of a matched-filter (35). The receiver uses received signal models of the various block linear equalizers that do not assume that each subchannel consists of several distinct paths. The receiver ertimates the impulse response characteristic of each subchannel as a whole.

Abstract translation: 使用类似于块线性均衡器中使用的接收信号的模型来减少脉冲响应干扰的接收机。 块线性均衡器包括去相关接收器，迫零接收器，最小均方误差接收器等。 本发明包括用于校正直接干扰消除器（39）的输出的干扰计算处理器反馈回路（43）。 迭代过程从匹配滤波器（35）的输出符号中去除干扰源。 接收机使用不假定每个子信道由几个不同路径组成的各种线性均衡器的接收信号模型。 接收机总体来说每个子信道的脉冲响应特性。

公开(公告)号：WO01028121A2

公开(公告)日：2001-04-19

申请号：PCT/IL2000/000645

申请日：2000-10-12

IPC: H04B1/707 ,  H04B1/7093 ,  H04L7/04 ,  H04L25/03 ,  H04L25/06 ,  H04L25/49 ,  H04L27/02 ,  H03B5/32

CPC classification number: H04L27/02 ,  H04B1/70712 ,  H04B1/7093 ,  H04L7/043 ,  H04L25/03834 ,  H04L25/06 ,  H04L25/4902

Abstract: A bidirectional direct sequence spread spectrum half-duplex RF modem. The RF modem can be applied to transmit and receive numerous types of analog and digital pulse modulation. The modem incorporates a SAW based correlator for performing the spreading and de-spreading functions in the transmitter and receiver. A SAW resonator fabricated on the same monolithic substrate provides the frequency source for the oscillator. An upconverter/downconverter provides frequency translation to the desired frequency band. Pulse gating and interrogating pulse shaping are employed to reduce the spectral side bands of the transmitted spread pulse. The RF modem operates as an analog or digital pulse transmitter and receiver. It is adapted to be generic and is versatile enough to be used in many different types of data communication systems, such as OOK, PWM and PPM. The RF modem can be used as the physical (PHY) layer in a layered communication system such as the ISO OSI communication stack. In an alternative embodiment, the transmission bit rate is increased by using a plurality of correlators wherein each is configured with a unique function (i.e., code) that is orthogonal with all other functions.

Abstract translation: 双向直接序列扩频半双工RF调制解调器。 RF调制解调器可以应用于发送和接收多种类型的模拟和数字脉冲调制。 调制解调器包括用于在发射机和接收机中执行扩展和解扩功能的基于SAW的相关器。 制造在同一单片基板上的SAW谐振器为振荡器提供频率源。 上变频器/下变频器提供频率转换到期望的频带。 采用脉冲选通和询问脉冲整形来减小发射扩展脉冲的频谱边带。 RF调制解调器作为模拟或数字脉冲发射器和接收器工作。 它适用于通用的，通用性足以用于许多不同类型的数据通信系统，如OOK，PWM和PPM。 RF调制解调器可以用作诸如ISO OSI通信栈的分层通信系统中的物理（PHY）层。 在替代实施例中，通过使用多个相关器来增加传输比特率，其中每个相关器配置有与所有其他功能正交的唯一功能（即，代码）。

公开(公告)号：WO00064066A1

公开(公告)日：2000-10-26

申请号：PCT/US2000/008187

申请日：2000-03-28

IPC: H04B1/7075 ,  H04B1/7093 ,  H04B1/7097 ,  H04B1/7115 ,  H04L7/10 ,  H04B1/707

CPC classification number: H04B1/7075 ,  H04B1/70754 ,  H04B1/7093 ,  H04B1/7097 ,  H04B1/7115

Abstract: A system and method are provided for achieving slot synchronization in a Wideband CDMA system in the presence of large initial frequency errors. A FSC matched filter having a reduced coherence window is provided for reducing degradation of a symbol due to carrier phase rotation resulting from oscillator error, thereby preventing severe loss of signal energy at the peaks of the FSC matched filter output. Additionally, a circular sliding integrator is provided to combine the accumulated disbursed signal energies due to the oscillator error and multipath interference, thereby allowing easier identification of the time index representing the time slot boundary. Further, a sorter is provided for determining a predetermined number of time index candidates representing the time slot boundary, thereby increasing the possibility that the true time index boundary is sent to the second stage of synchronization.

Abstract translation: 提供一种用于在存在大的初始频率误差的情况下在宽带CDMA系统中实现时隙同步的系统和方法。 提供了具有减小的相干窗口的FSC匹配滤波器，用于减少由于振荡器误差引起的载波相位旋转引起的符号劣化，从而防止FSC匹配滤波器输出峰值处的信号能量严重丧失。 此外，提供圆形滑动积分器以由于振荡器误差和多径干扰而组合累积的分支信号能量，从而允许更容易地识别表示时隙边界的时间指标。 此外，提供了一种分类器，用于确定表示时隙边界的预定数量的时间索引候选，从而增加了将真实时间索引边界发送到第二阶段同步的可能性。