公开(公告)号：WO1990003610A1

公开(公告)日：1990-04-05

申请号：PCT/US1989004098

申请日：1989-09-19

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  BRENDER, Ronald, F. ,  BRETT, Bevin, R.

IPC: G06F09/45

CPC classification number: G06F8/447

Abstract: A compiler maintains a library of sharable program structures generated in response to instantiations of a generic program structure, along with characteristics of parameters which were used in generating the sharable program structure. In response to an instantiation of a generic program structure, the compiler generates information relating to the characteristics and usage of each parameter which are used in connection with the instantiation. The compiler then compares that information to the corresponding informaton associated with the sharable program structures in the library. If the library contains a sharable program structure whose parameter information compares satisfactorily, that sharable program structure is used in connection with further operations in connection with the instantiation. On the other hand, if the library does not contain such a sharable program structure, one is generated and stored in the library, along with the characteristics of the parameters used in its generation, for use in sharing with later instantiations. In addition, the just-generated sharable program structure is used in further operations in connection with the instantiation.

Abstract translation: 编译器维护响应于通用程序结构的实例生成的可共享程序结构的库，以及用于生成可共享程序结构的参数的特性。 响应于通用程序结构的实例化，编译器生成与实例化结合使用的每个参数的特性和使用相关的信息。 然后，编译器将该信息与库中可共享程序结构相关联的相应信息进行比较。 如果库包含可共享的程序结构，其参数信息令人满意地进行比较，则可共享程序结构与实例化相关的进一步操作结合使用。 另一方面，如果库不包含这样一个可共享的程序结构，则生成并存储在库中，以及其生成中使用的参数的特征，以便与后续实例化共享。 另外，刚才生成的可共享程序结构用于与实例化相关的进一步操作。

公开(公告)号：WO1990000290A1

公开(公告)日：1990-01-11

申请号：PCT/US1989002885

申请日：1989-06-29

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  TSENG, Mitchell, M. ,  ORIUCH, Edmund, P. ,  HAYDEN, Bruce ,  SCHAEFER, John ,  SAND, Erik ,  VELEZ, Nelson ,  WILLSTEAD, Beth

IPC: G06F15/60

CPC classification number: G06F17/5009

Abstract: A simulator including a process model processor which processes a mathematical model of a physical system in connection with input data and a heuristic knowledge base controlled by an inference engine. In addition to the input data, from time to time during processing of the mathematical model, the process model requires heuristic knowledge from the heuristic knowledge base. At such times, the process model processor suspends processing of the mathematical model and enables the inference engine to obtain the required heuristic knowledge and transfer it to the process model processor. Upon receiving the heuristic knowledge, the process model processor resumes processing of the mathematical model.

Abstract translation: 一种模拟器，包括处理与输入数据有关的物理系统的数学模型的过程模型处理器和由推理机控制的启发式知识库。 除了输入数据之外，在数学模型的处理期间，过程模型还需要启发式知识库的启发式知识。 在这种时候，过程模型处理器暂停数学模型的处理，并且使得推理机能够获得所需的启发式知识并将其传送到过程模型处理器。 在接收到启发式知识后，过程模型处理器恢复数学模型的处理。

公开(公告)号：WO1989009964A1

公开(公告)日：1989-10-19

申请号：PCT/US1989001586

申请日：1989-04-14

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  GAMACHE, Rodney, N. ,  FARNHAM, Stuart, J. ,  HARVEY, Michael, S.

IPC: G06F09/46

CPC classification number: G06F9/4831 ,  G06F9/52

Abstract: The supply of available tasks that may be executed by a blocked processor while it is waiting for the end of a conflict with another processor, is controlled by temporarily lowering the interrupt priority to a minimum level above which it will be permitted to accept other tasks for execution.

Abstract translation: 当等待结束与另一个处理器的冲突时，阻塞的处理器可能执行的可用任务的提供是通过将中断优先级暂时降低到最低级别来控制的，在该最低级别以下，允许其接受其他任务 执行。

公开(公告)号：WO1989008327A1

公开(公告)日：1989-09-08

申请号：PCT/US1989000732

申请日：1989-02-28

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  FOX, Leslie, R.

IPC: H01L23/40

CPC classification number: H01L23/585 ,  H01L23/16 ,  H01L23/4006 ,  H01L23/42 ,  H01L2023/4043 ,  H01L2023/4062 ,  H01L2023/4068 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaging and cooling assembly for integrated circuit chips includes a base (14) for reception of one or more circuit chips (12), and a combination heat sink and cover (28) for attachment to the base (19). The circuit chips (12) are mounted circuit side down on the base (14), and include flexible lead frames (20) for attachment to bonding pads on the base (14). Compliant cushions (44) that generally conform to the shape and size of the chips (12) are held loosely between the circuit sides of the chips, and the base (14). The heat sink (28) engages the back sides of the circuit chips (12) when it is attached to the base. This causes the chips (12) to compress the compliant cushions (44), thereby holding the chips firmly in position, and forming a high thermal conductivity interface between the chips and the heat sink (28). To further enhance the heat transfer characteristics of the interface, a thin film of fluid (50) is coated on the back sides of each chip (12) to fill in the microvoids which result from asperity contact of the heat sink (28) and chip mating surfaces. A sealing gasket (34) is provided between the heat sink (28) and the base (14) to form a protective enclosure for the chips. Intermediate housings or heat spreader structures may alternatively be disposed between the chips (12) and the heat sink (28).

Abstract translation: 用于集成电路芯片的封装和冷却组件包括用于接收一个或多个电路芯片（12）的基座（14）和用于附接到基座（19）的组合散热器和盖子（28）。 电路芯片（12）侧面安装在基座（14）上，并且包括用于附接到基座（14）上的接合焊盘的柔性引线框架（20）。 通常符合芯片（12）的形状和尺寸的合适的衬垫（44）松散地保持在芯片的电路侧和基座（14）之间。 当散热器（28）附接到基座时，散热器（28）接合电路芯片（12）的背面。 这使得芯片（12）压缩顺应性衬垫（44），从而将芯片牢固地保持就位，并且在芯片和散热器（28）之间形成高导热性界面。 为了进一步提高界面的传热特性，在每个芯片（12）的背面上涂覆有薄膜（50），以填充由散热器（28）和芯片（28）的凹凸接触所产生的微孔 配合面。 密封垫圈（34）设置在散热器（28）和基座（14）之间，以形成用于芯片的保护外壳。 中间壳体或散热器结构可替代地设置在芯片（12）和散热器（28）之间。

公开(公告)号：WO1989006011A1

公开(公告)日：1989-06-29

申请号：PCT/US1988004418

申请日：1988-12-14

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  NIELSEN, Michael, J., K.

IPC: G06F09/46

CPC classification number: G06F9/52 ,  G06F13/36

Abstract: Interlocking of addresses in a system with parallel processors using a common memory space (15) is managed by maintaining for each processor a record of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is analyzed against the lock state record (31), and the processor's request for access to an intercommunication bus is transmitted only when the lock state of the system is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record (31) of each processor is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.

Abstract translation: 通过为每个处理器维护系统的锁定状态的记录来管理具有使用公共存储器空间（15）的并行处理器的系统中的地址的联锁。 当处理器寻求启动事务时，针对锁定状态记录（31）分析事务，并且只有当系统的锁定状态处于事务处理条件时才传送处理器访问互通总线的请求。 通过监视和分析总线事务，每个处理器的锁状态记录（31）保持最新。 因此，在要求总线之前，因此阻止涉及锁定地址的事务，避免了无效活动中的公共汽车的捆绑。

公开(公告)号：WO1989003562A1

公开(公告)日：1989-04-20

申请号：PCT/US1988003570

申请日：1988-10-13

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  KENT, Allan, R. ,  READ, Harold, A. ,  HENRY, Barry, A. ,  KACZOR, Charles, E. ,  MILLS, Milton, V. ,  CARN, Ronald, C. ,  METZ, Donald, R. ,  ZAGAME, Steven, P. ,  KIRK, Robert, C.

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F11/2007 ,  G06F11/22

Abstract: A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added. The coupler also includes a plurality of timers which determine fault conditions, and a diagnostic processor monitors the timers and associated error flags to diagnose faults to the board level. The conditions existing at the time of fault diagnosis are written into a non-volatile memory located on the circuit board. Therefore, the information is physically carried along with the board to the repair facility.

公开(公告)号：WO1989002123A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002898

申请日：1988-08-23

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  RIGGLE, Michael, C. ,  WENG, Lih-Jyh ,  HUI, Pak, Ning

IPC: G06F11/10

CPC classification number: H03M13/151

Abstract: A VLSI circuit (10) that implements a symmetric Reed-Solomon error correcting code for correcting up to 32 symbol errors per code word in real time. Extensive use of data pipelining (16), (18), (20) and novel solutions to the Berlekamp-Massey algorithm without supplementary software or heavily iterative hardware calculations provide a high bandwidth, low latency implementation of the Reed-Solomon code with low data overhead and low hardware cost.

Abstract translation: 实现对称Reed-Solomon纠错码的VLSI电路（10），用于每个码字实时校正多达32个符号错误。 数据流水线（16），（18），（20）和Berlekamp-Massey算法的新颖解决方案，无需补充软件或大量迭代硬件计算，可提供具有低数据量的Reed-Solomon码的高带宽，低延迟实现 架空和低硬件成本。

公开(公告)号：WO1989002119A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002923

申请日：1988-08-24

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  PENG, Victor ,  BOWHILL, William, Johnson ,  GAVRIELOV, Nachem, Mosche

IPC: G06F07/48

CPC classification number: G06F7/74 ,  G06F7/485 ,  G06F7/49952

Abstract: In a floating point addition or subtraction procedures, two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand arguments so that the addition or subtraction procedure between the operand fractions can be performed. In order to complete the associated computations correctly, it is necessary to know if any of the fraction positions removed from the fraction by the shift operation include non-zero signals, i.e., the operation referred to as computation of the ''sticky'' bit. The second important shift operation occurs after the addition or subtraction of the operand fractions has taken place. The interim resulting operand fraction must be normalized, i.e., a non-zero signal is placed in the most significant operand fraction bit position and the operand exponent argument adjusted accordingly. In order to accomplish this normalization, the position of the leading one (most significant non-zero) bit must be identified. The present invention utilizes a carry chain both for computing the ''sticky'' bit information and for detecting the leading one in an operand fraction.

公开(公告)号：WO1989001688A1

公开(公告)日：1989-02-23

申请号：PCT/US1988002710

申请日：1988-08-08

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  LEE, Neville, K., S. ,  HOWARD, James

IPC: G11B11/10

CPC classification number: G11B11/10532

Abstract: An optical mass storage device for use in data processing systems. Two or more lasers provide separate read and write laser beams having different wavelengths. The read and write laser beams can be orthogonally polarized. A polarizing beam splitter (30) combines the read and write beams along a common optical path to an optical head (12). The head directs the combined beam to a magneto-optic storage medium (10). A read beam is reflected back by the medium (10) to the common path through the head (12). A dichroic beam splitter (32) disposed in the common path between the head (12) and the polarizing splitter (30) reflects the read beam to an optical detector (18a, 18b, 20). If more than one write laser is necessary, a second dichroid splitter (68) can be used to combine the multiple write beams and the read beam.

Abstract translation: 一种用于数据处理系统的光学海量存储装置。 两个或更多个激光器提供具有不同波长的单独的读和写激光束。 读写激光束可以是正交极化的。 偏振光束分离器将沿着公共光路的读取和写入光束组合到光学头。 头部将组合的光束引导到磁光存储介质。 读取光束被介质反射回通过头部的公共路径。 设置在头部和偏振分离器之间的公共路径中的二向色分束器将读取的光束反射到光学检测器。 如果需要多于一个写入激光器，则可以使用第二分色器来组合多个写入光束和读取光束。

公开(公告)号：WO1988007741A1

公开(公告)日：1988-10-06

申请号：PCT/US1988000908

申请日：1988-03-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  DAS, Shyam

IPC: G11B05/39

CPC classification number: G11B5/3925 ,  G11B5/09 ,  G11B5/11 ,  G11B5/3903 ,  G11B5/3954 ,  G11B5/398 ,  G11B2005/0008

Abstract: A read/write head for use in a magnetic storage device in a digital data processing system for writing data in the form of magnetic flux onto, and reading data from a spinning magnetic disk. The head has two magnetic pole pieces (11, 12) each with a yoke region (13) which tapers to a pole tip (14) and an energizable coil (16) situated between the pole pieces in the yoke region for generating magnetic flux. One of the pole pieces has a slot (17) in the yoke region, and a strip (20) of magneto-resistive material is situated adjacent the slot. The magneto-resistive strip is adapted to be connected to sensing equipment which measures variations in the resistance of the magneto-resistive strip in response to the variations in the magnetic flux recorded on the media. Several slots may be formed in the pole pieces, and an elongated magneto-resistive strip (42) may be situated adjacent the slots.

Abstract translation: 一种用于数字数据处理系统中的磁存储装置的读/写头，用于以磁通量的形式将数据写入到旋转磁盘上并从旋转磁盘读取数据。 头部具有两个磁极片（11,12），每个磁极片具有对磁极尖端（14）逐渐变细的磁轭区域（13）和位于磁轭区域中的极靴之间的可激励线圈（16），用于产生磁通量。 极片中的一个在磁轭区域中具有槽（17），并且磁阻材料的带（20）位于槽附近。 磁阻带适于连接到感测设备，该感测设备测量响应于记录在介质上的磁通量的变化的磁阻带的电阻的变化。 可以在极片中形成多个槽，并且细长的磁阻条（42）可以位于槽附近。