公开(公告)号：WO2003101083A2

公开(公告)日：2003-12-04

申请号：PCT/US2002/031647

申请日：2002-10-02

Applicant: THREE-FIVE SYSTEMS, INC. ,  WATERMAN, John, Karl

Inventor： WATERMAN, John, Karl

IPC: H04N

CPC classification number: G09G5/005 ,  G09G5/006 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G2360/128 ,  H04N5/907 ,  H04N7/0132 ,  H04N2005/745

Abstract: A memory management circuit manages frame data for a display system such as used in a projection television system or cellular phone. The frame data includes frames corresponding to a series of images for viewing by a user. The memory manager includes an input buffer to receive the frame data, a memory interface coupled to receive the frame data from the input buffer, and an output buffer coupled to receive the frame data from the memory interface and output the frame data to a display such as a liquid crystal (LCD) micro-display. The memory interface sends and receives the frame data as packets, with each packet having a size less than a full frame, to and from an external memory able to store at least one full frame of data.

Abstract translation: 存储器管理电路管理诸如在投影电视系统或蜂窝电话中使用的显示系统的帧数据。 帧数据包括与一系列用于用户观看的图像相对应的帧。 存储器管理器包括用于接收帧数据的输入缓冲器，耦合以从输入缓冲器接收帧数据的存储器接口，以及耦合到从存储器接口接收帧数据的输出缓冲器，并将帧数据输出到诸如 作为液晶（LCD）微显示器。 存储器接口发送和接收帧数据作为分组，其中每个分组具有小于全帧的大小，能够存储能够存储至少一个全帧数据的外部存储器。

公开(公告)号：WO2003067317A1

公开(公告)日：2003-08-14

申请号：PCT/KR2002/001375

申请日：2002-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  LEE, Baek-Woon

Inventor： LEE, Baek-Woon

IPC: G02F1/133

CPC classification number: G09G3/2092 ,  G09G3/3611 ,  G09G2360/121 ,  G09G2360/128 ,  G09G2360/18

Abstract: A liquid crystal display according to the present invention includes a gray signal modifier connected with a frame memory outputting and storing data by a burst mode. The gray signal modifier receives a gray signal of current frame from a data gray signal source and stores it in the frame memory by the burst mode, and reads a gray signal of previous frame stored in the frame memory to generate and output a modified gray signal in consideration of a gray signal of current frame and a gray signal of previous frame. Data pins and instruction pins of the frame memory share buses interfacing with the gray signal modifier.

Abstract translation: 根据本发明的液晶显示器包括与通过突发模式输出和存储数据的帧存储器连接的灰度信号修改器。 灰度信号修改器从数据灰度信号源接收当前帧的灰度信号，并通过突发模式将其存储在帧存储器中，并且读取存储在帧存储器中的先前帧的灰度信号以产生并输出修改的灰度信号 考虑到当前帧的灰度信号和前一帧的灰度信号。 帧存储器的数据引脚和指令引脚共享与灰度信号修改器连接的总线。

公开(公告)号：WO00000959A1

公开(公告)日：2000-01-06

申请号：PCT/KR1999/000008

申请日：1999-01-04

IPC: G09G3/28 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  H04N5/66

CPC classification number: G09G5/393 ,  G09G3/28 ,  G09G5/399 ,  G09G2310/0224 ,  G09G2360/12 ,  G09G2360/128

Abstract: A method of writing N/K groups of non-interlaced video data and reading the same, in/from SDRAM used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data and reading the same is described. First, a first bank of the SDRAM is divided into L/2 number of column regions for storing upper L/2 number of weight data according to weights, respectively. Second, a second bank of the SDRAM is divided into L/2 number of column regions for storing lower L/2 number of weight data according to their weight, respectively. Third, the N/K groups of non-interlaced video data corresponding to M vertical line are written into respective column regions in M row of the first and second banks according to the weights, wherein N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data. Accordingly, in writing the video data based on the non-interlaced scanning method on a frame memory using the SDRAM which is relatively cheap and reading the video data from the frame memory, since a burst write or burst read operation is allowed, the configuration of the write or read address generator can be simplified.

Abstract translation: 在PDP类型TV接收机中用作帧存储器的SDRAM中写入N / K组非隔行视频数据并读取它们的方法，其中一帧包括N×M个像素，每个像素被采样 L比特，然后K个样本由L个加权数据重新排序，并且读取相同的描述。 首先，SDRAM的第一组被分成L / 2个列区域，用于分别根据权重存储上L / 2个权重数据。 其次，SDRAM的第二组分为L / 2数量的列区域，用于分别存储较低的L / 2数量的权重数据。 第三，根据权重，将对应于M垂直线的N / K组的非隔行视频数据写入第一和第二组的M行的相应列区域，其中N是水平像素的数量，M是 垂直线数，L是子场数，K是权重数据的位数。 因此，在使用相对廉价的SDRAM并且从帧存储器读取视频数据的帧存储器上，基于非隔行扫描方法将视频数据写入帧存储器，由于允许突发写入或突发读取操作，因此， 可以简化写或读地址生成器。

公开(公告)号：WO1997039437A1

公开(公告)日：1997-10-23

申请号：PCT/US1997005983

申请日：1997-04-11

Applicant: INTERGRAPH CORPORATION

Inventor： INTERGRAPH CORPORATION ,  BUCKELEW, Matt, E. ,  CARLTON, Stewart, G. ,  DEMING, James, L. ,  FARMER, Michael, S. ,  HEINRICH, Steven, J. ,  MOSLEY, Mark, A. ,  WHITMORE, Clifford, A.

IPC: G09G01/16

CPC classification number: G09G5/363 ,  G09G5/022 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G2360/12 ,  G09G2360/121 ,  G09G2360/123 ,  G09G2360/128 ,  G11C7/1015 ,  G11C7/1018 ,  G11C8/00 ,  G11C8/04

Abstract: In standard display systems pixel data are stored in the frame buffer such that all data related to a pixel (both intensity values and non-display data as masks, Fast Clear etc.) are stored in a memory word; consecutive pixels of a line are stored in subsequent memory words. This data arrangement causes several memory accesses to be necessary for operations as drawing etc. on a set of neighbouring pixels. The present invention speeds up such operations by subdividing the display area in (rectangular) blocks, whose pixel data are stored in corresponding blocks of subsequent memory words. For each pixel, display data only are stored in a block, and non-display data are stored elsewhere, so that burst access mode can be used for accessing a set of neighbouring pixel display data in a single operation. The arrangement based on rectangular blocks is particularly advantageous for writing triangles, vectors etc. Each block is preferably stored across interleaved memory banks, that may be accessed in parallel for rendering and display. Dual bank operation (opening two pages at once) can be effected according to a checker-board block allocation, which still improves triangle and vector management. The invention is particularly suitable for SDRAM arrays having a single access port.

Abstract translation: 在标准显示系统中，将像素数据存储在帧缓冲器中，使得与像素（强度值和非显示数据作为掩码，快速清除等）相关的所有数据都存储在存储器字中; 一行的连续像素被存储在随后的存储字中。 该数据排列导致对一组相邻像素上的绘图等操作需要几个存储器访问。 本发明通过将（矩形）块中的显示区域细分，将其像素数据存储在后续存储字的相应块中来加速这种操作。 对于每个像素，仅显示数据被存储在块中，并且非显示数据被存储在别处，使得突发存取模式可用于在单个操作中访问一组相邻像素显示数据。 基于矩形块的布置对于写入三角形，向量等是特别有利的。每个块优选地存储在交叉存储器组之间，可以并行访问以进行渲染和显示。 双行操作（一次打开两页）可以根据棋盘块分配进行，这仍然可以改善三角形和矢量管理。 本发明特别适用于具有单个访问端口的SDRAM阵列。

公开(公告)号：WO1997026604A1

公开(公告)日：1997-07-24

申请号：PCT/US1997000014

申请日：1997-01-15

Applicant: MONOLOTHIC SYSTEM TECHNOLOGY, INC.

Inventor： MONOLOTHIC SYSTEM TECHNOLOGY, INC. ,  HSU, Fu-Chieh

IPC: G06F15/167

CPC classification number: G09G5/363 ,  G06F15/17 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/123 ,  G09G2360/125 ,  G09G2360/126 ,  G09G2360/128

Abstract: A computer unified memory architecture (UMA) (300) system and method which includes a unified memory (304) which is partitioned into a main memory (304a) and a main frame buffer memory (304b). Together, the main frame buffer memory and the expansion frame buffer memory (306) form an entire frame buffer memory. The UMA system performs a display refresh operation by alternately accessing the main frame buffer memory and the expansion frame buffer memory. Because the display data bandwidth is split between the main frame buffer memory and the expansion frame buffer memory, the data bandwidth of the unified memory is effectively increased, thereby enabling higher system performance. The expansion frame buffer memory has a relatively small capacity, thereby retaining much of the cost benefit of a UMA system.

Abstract translation: 一种计算机统一存储器架构（UMA）（300）系统和方法，包括分为主存储器（304a）和主帧缓冲存储器（304b）的统一存储器（304）。 一起，主帧缓冲存储器和扩展帧缓冲存储器（306）组成整个帧缓冲存储器。 UMA系统通过交替访问主帧缓冲存储器和扩展帧缓冲存储器来执行显示刷新操作。 由于显示数据带宽分散在主帧缓冲存储器和扩展帧缓冲存储器之间，所以统一存储器的数据带宽有效提高，从而实现更高的系统性能。 扩展帧缓冲存储器具有相对较小的容量，从而保留了UMA系统的大部分成本优势。

公开(公告)号：WO1996036037A1

公开(公告)日：1996-11-14

申请号：PCT/US1996006438

申请日：1996-05-08

Applicant: THE 3DO COMPANY

Inventor： THE 3DO COMPANY ,  THAIK, Richard, W. ,  MICAL, Robert, Joseph ,  LANDRUM, Stephen, Harland ,  WASSERMAN, Steve, C. ,  NEEDLE, David, Lewis ,  CARROLL, Tina, L.

IPC: G09G05/36

CPC classification number: G09G5/026 ,  G09G3/2051 ,  G09G5/001 ,  G09G5/06 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G2360/121 ,  G09G2360/126 ,  G09G2360/128

Abstract: Method and apparatus (150) for managing color modification of a raster based image on a real time, line-by-line basis, or pixel-by-pixel basis in response to pixel information (140/141) and control information (142/143) stored in memory (130/131).

Abstract translation: 用于响应于像素信息（140/141）和控制信息（142/141）逐个基于逐个或逐个像素地管理基于光栅的图像的颜色修改的方法和装置（150） 143）存储在存储器（130/131）中。

公开(公告)号：WO2018080625A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/048030

申请日：2017-08-22

Applicant: QUALCOMM INCORPORATED

Inventor： WANG, Chun

IPC: G09G5/42 ,  G06F3/14 ,  G09G5/397 ,  G09G5/14

CPC classification number: G06T1/20 ,  G06F3/1446 ,  G06T1/60 ,  G06T11/00 ,  G06T11/60 ,  G09G5/14 ,  G09G5/397 ,  G09G5/42 ,  G09G2300/026 ,  G09G2340/02 ,  G09G2340/12 ,  G09G2352/00 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/122 ,  G09G2360/128 ,  G09G2360/18

Abstract: In general, techniques are described for performing multi-layer image fetching using a single hardware image fetcher pipeline of a display processor (18). A device comprising a layer buffer (26), and a display processor (18) may be configured to perform Direct Memory Access (DMA) techniques. The layer buffer (26) may be configured to store two or more independent layers (27A-27N), each layer representing either a seperate, independent image, or a portion of a seperate, independent image. The display processor may include a single hardware image fetcher pipeline. The single hardware image fetcher pipeline, through the use of two or more image fetchers (24A-24N), may be configured to concurrently retrieve two or more independent layers (27A-27N) from the layer buffer (26). Content of the layers are then concurrently processed (28, 30A-30N) and output by two or more outputs (38) of the single hardware image fetcher pipeline. A composition formed from the two or more processed independent layers form one of the frames to be displayed by one or more display units.

Abstract translation: 通常，描述了使用显示处理器（18）的单个硬件图像获取器管线来执行多层图像获取的技术。 包括层缓冲器（26）和显示处理器（18）的设备可以被配置为执行直接存储器访问（DMA）技术。 层缓冲器（26）可以被配置为存储两个或更多个独立层（27A-27N），每个层表示单独的独立图像或者独立图像的一部分。 显示处理器可以包括单个硬件图像获取器管线。 通过使用两个或更多个图像获取器（24A-24N），单个硬件图像获取器管线可以被配置为从层缓冲器（26）并发地检索两个或更多个独立层（27A-27N）。 然后同时处理层的内容（28,30A-30N）并且由单个硬件图像获取器管线的两个或更多个输出（38）输出。 由两个或多个处理过的独立层形成的构图形成了要由一个或多个显示单元显示的一个帧。

公开(公告)号：WO2014209408A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048812

申请日：2013-06-29

Applicant: INTEL CORPORATION ,  SHARMA, Sameer ,  WANG, Hui ,  MIAO, Deguo

Inventor： SHARMA, Sameer ,  WANG, Hui ,  MIAO, Deguo

IPC: G06F1/16 ,  G06F3/14

CPC classification number: G06F1/1649 ,  G06F1/162 ,  G06F1/1641 ,  G06F1/1647 ,  G06F1/165 ,  G06F1/1654 ,  G06F3/1438 ,  G06F3/1462 ,  G09G2360/121 ,  G09G2360/128

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer, laptop, or tablet that includes a circuit board coupled to a plurality of electronic components (which may include any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include establishing an electrical coupling between a first portion of an electrical device and a second portion of the electrical device, where the first portion includes a first display and the second portion includes a second display. Removing the first portion from the second portion permits the first portion and the second portion to each operate as a standalone tablet device. The example implementation may also include initiating a collaboration session when the first portion is removed from the second portion.

Abstract translation: 本文描述的特定实施例提供了一种电子设备，例如笔记本电脑，膝上型计算机或平板电脑，其包括耦合到多个电子组件（其可以包括任何类型的组件，元件，电路等）的电路板。 电子设备的一个具体示例实现可以包括在电气设备的第一部分和电气设备的第二部分之间建立电耦合，其中第一部分包括第一显示器，并且第二部分包括第二显示器。 从第二部分移除第一部分允许第一部分和第二部分各自作为独立的平板装置操作。 示例实现还可以包括当第一部分从第二部分移除时启动协作会话。

公开(公告)号：WO2011163138A1

公开(公告)日：2011-12-29

申请号：PCT/US2011/041100

申请日：2011-06-20

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  MATHEW, Mithran, Cheriyan

Inventor： MATHEW, Mithran, Cheriyan

IPC: G06F3/14 ,  H04N7/34 ,  H04N7/36

CPC classification number: G09G5/003 ,  G06F3/1415 ,  G09G5/393 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/122 ,  G09G2360/128 ,  G09G2370/12 ,  G09G2370/16 ,  H04N19/507 ,  H04N19/593

Abstract: Disclosed are methods, apparatus, and systems, including computer program products, implementing and using techniques for processing frames of video data sent across a display interface using a block-based encoding scheme and a tag ID. The disclosed techniques provide for optimization of the display interface situated between the graphics processor and the display controller of an electronic device. The disclosed techniques minimize the amount of signaling over the interface and reduce the power consumed at the interface. Accordingly, the battery life of some electronic devices can be extended. In one embodiment, the graphics processor is configured to receive frames of video data, where each frame includes one or more blocks of the video data. The graphics processor is configured to encode each block of video data, generate a tag ID associated with each encoded block of video data, and output each encoded block of video data and associated tag ID. The display controller is configured to receive the encoded blocks of video data and associated tag ID's from the graphics processor via the display interface. The display controller is configured to interpret the tag ID associated with a respective encoded block of video data and determine whether to decode at least part of the respective encoded block of video data according to the tag ID. A display, such as a memory-based display, is in communication with the display controller. The display is configured to receive and display decoded blocks of video data from the display controller.

Abstract translation: 公开了包括计算机程序产品在内的方法，装置和系统，其使用基于块的编码方案和标签ID来实现和使用通过显示接口发送的视频数据帧的技术。 所公开的技术提供了位于图形处理器和电子设备的显示控制器之间的显示界面的优化。 所公开的技术使接口上的信令量最小化并减少接口处的功耗。 因此，可以延长一些电子设备的电池寿命。 在一个实施例中，图形处理器被配置为接收视频数据帧，其中每帧包括视频数据的一个或多个块。 图形处理器被配置为对视频数据的每个块进行编码，生成与每个编码的视频数据块相关联的标签ID，并且输出每个经编码的视频数据块和相关联的标签ID。 显示控制器被配置为经由显示接口从图形处理器接收编码的视频数据块和相关联的标签ID。 显示控制器被配置为解释与相应编码的视频数据块相关联的标签ID，并根据标签ID确定是否解码相应编码的视频数据块的一部分。 诸如基于存储器的显示器的显示器与显示控制器通信。 显示器被配置为从显示控制器接收和显示解码的视频数据块。

公开(公告)号：WO2008070576A3

公开(公告)日：2009-04-30

申请号：PCT/US2007086173

申请日：2007-11-30

Applicant: MOSYS INC ,  PATEL MUKESH K ,  LEUNG WINGYU

Inventor： PATEL MUKESH K ,  LEUNG WINGYU

IPC: G06F12/00

CPC classification number: G09G5/36 ,  G06F3/14 ,  G09G5/001 ,  G09G5/18 ,  G09G5/363 ,  G09G5/39 ,  G09G2330/021 ,  G09G2360/12 ,  G09G2360/125 ,  G09G2360/128

Abstract: A memory device incorporating a multi-media accelerator and an embedded memory, wherein the memory device operates as a standard stand-alone memory when the multi-media accelerator is not enabled. The memory device includes a memory interface that is compatible with multiple types of memory controllers, thereby enabling multiple types of external devices to interact with the multi-media accelerator and access the embedded memory. The embedded memory can be shared between external devices and multi-media devices.

Abstract translation: 一种结合了多媒体加速器和嵌入式存储器的存储器件，其中当多媒体加速器未启用时，存储器件作为标准独立存储器运行。 存储器件包括与多种类型的存储器控​​制器兼容的存储器接口，从而使多种类型的外部设备与多媒体加速器交互并访问嵌入式存储器。 嵌入式存储器可以在外部设备和多媒体设备之间共享。