公开(公告)号：WO0176129A3

公开(公告)日：2002-05-23

申请号：PCT/US0109714

申请日：2001-03-27

Applicant: GEN DYNAMICS DECISION SYSTEMS

Inventor： CARSWELL PHILLIP ANTHONY

IPC: G06F1/00 ,  G06F9/38 ,  G06F21/72 ,  H04L9/00 ,  H04L9/06

CPC classification number: G06F9/3879 ,  G06F21/72 ,  H04L9/0618 ,  H04L2209/125

Abstract: A cryptographic engine (10) that includes a scalable cryptographic coprocessor (14) that is controlled by, and separate from, a main engine processor (12). The coprocessor includes a register bank (40) for receiving and storing data packets to be encrypted, and cryptographic processing slices (34a-34n) coupled to the register bank (40) with a processing capacity that is scalable based on application-specific parameters. The coprocessor (14) also includes a control device (38) coupled to the register bank (40) and the cryptographic processing device (34a-34n) for instructing the cryptographic processing slices to perform a cryptographic processing operation unique to each cryptographic processing slice (34a-34n) based on externally-received processing instructions.

Abstract translation: 一种加密引擎（10），其包括由主引擎处理器（12）控制和分离的可扩展密码协处理器（14）。 协处理器包括用于接收和存储要加密的数据分组的寄存器组（40）和耦合到寄存器组（40）的加密处理片（34a-34n），其具有基于应用特定参数可扩展的处理能力。 协处理器（14）还包括耦合到寄存器组（40）和密码处理设备（34a-34n）的控制设备（38），用于指示密码处理片段执行每个密码处理片（“ 34a-34n）基于外部接收的处理指令。

公开(公告)号：WO01093015A1

公开(公告)日：2001-12-06

申请号：PCT/GB2001/002354

申请日：2001-05-25

IPC: G06F7/72 ,  G09C1/00

CPC classification number: G06F7/724 ,  H04L9/002 ,  H04L9/0662 ,  H04L9/3093 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/34

Abstract: Parallel modulo arithmetic calculations are carried out on a device adapted to perform bitwise logical operations by storing the numbers to be operated upon in a vector form, and performing arithmetical operations on multiple numbers in parallel. The invention finds particular application in cryptosystems, as well as in other fields.

Abstract translation: 在适于通过以矢量形式存储待操作的数字并且并行执行多个数字的算术运算的适于执行逐位逻辑运算的装置上进行并行模运算计算。 本发明特别适用于密码系统以及其他领域。

公开(公告)号：WO01088692A2

公开(公告)日：2001-11-22

申请号：PCT/US2001/014616

申请日：2001-05-07

IPC: G06F1/00 ,  G06F7/72 ,  G06F9/38 ,  G06F21/00 ,  G06F7/52

CPC classification number: G06F9/3879 ,  G06F7/728 ,  G06F21/123 ,  G06F21/72 ,  H04L9/0877 ,  H04L2209/125

Abstract: Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output. An accumulator is configured to add the first vector multiplier output, and the second vector multiplier output, to produce a product output. The latency of Montgomery multiplication thereby can be reduced to nearly the latency of a single scalar multiplication.

Abstract translation: 蒙哥马利乘数和方法将残差被乘数乘以残差乘数，使用标量乘法器，第一向量乘法器和第二向量乘法器来获得残差乘积。 控制器被配置为使用乘法器的选定数字和矢量乘以模数和被乘数来控制标量乘法器，第一向量乘法器和第二向量乘数以重叠标量乘法。 标量乘法器被配置为将乘法器的最低有效位乘以乘法器的第一选定位数，以产生标量乘法器输出。 第一个向量乘法器被配置为将标量乘法器输出乘以模数，以产生第一向量乘法器输出。 第二向量乘法器被配置为将乘法器的第二选定位乘以被乘数，以产生第二向量乘法器输出。 累加器被配置为添加第一向量乘法器输出和第二向量乘数输出以产生乘积输出。 因此，蒙哥马利乘法的延迟可以降低到单个标量乘法的几乎等待时间。

公开(公告)号：WO01076129A2

公开(公告)日：2001-10-11

申请号：PCT/US2001/009714

申请日：2001-03-27

IPC: G06F1/00 ,  G06F9/38 ,  G06F21/72 ,  H04L9/00

CPC classification number: G06F9/3879 ,  G06F21/72 ,  H04L9/0618 ,  H04L2209/125

Abstract: A cryptographic engine (10) that includes a scalable cryptographic coprocessor (14) that is controlled by, and separate from, a main engine processor (12). The coprocessor includes a register bank (40) for receiving and storing data packets to be encrypted, and a cryptographic processing device (34a-34n) coupled to the register bank (40) with a processing capacity that is scalable based on application-specific parameters. The coprocessor (14) also includes a control device (38) coupled to the register bank (40) and the cryptographic processing device (34a-34n) for instructing the cryptographic processing device to perform a cryptographic processing operation unique to the cryptographic processing device (34a-34n) based on externally-received processing instructions.

Abstract translation: 一种加密引擎（10），其包括由主引擎处理器（12）控制和分离的可扩展密码协处理器（14）。 协处理器包括用于接收和存储要加密的数据分组的寄存器组（40）和耦合到寄存器组（40）的加密处理设备（34a-34n），处理能力基于应用特定参数可扩展 。 协处理器（14）还包括耦合到寄存器组（40）和密码处理设备（34a-34n）的控制设备（38），用于指示密码处理设备执行密码处理设备唯一的密码处理操作（ 34a-34n）基于外部接收的处理指令。

公开(公告)号：WO01061912A1

公开(公告)日：2001-08-23

申请号：PCT/US2001/004599

申请日：2001-02-13

IPC: H04L9/32 ,  H04L29/06 ,  H04L9/00

CPC classification number: H04L63/0442 ,  H04L9/0643 ,  H04L63/0485 ,  H04L63/0823 ,  H04L63/123 ,  H04L63/164 ,  H04L2209/04 ,  H04L2209/125 ,  H04L2209/38

Abstract: A method, apparatus, and article of manufacture for a computer implemented packet processor. The packet processor (104) processes packets in parallel. In particular, the packet processor performs a combination of encryption (108) and authentication (110) on data packets. The encryption and authentication processing of a second data packet may begin before the encryption and authorization processes of a first data packet have completed.

Abstract translation: 一种用于计算机实现的分组处理器的方法，装置和制品。 分组处理器（104）并行处理分组。 特别地，分组处理器对数据分组执行加密（108）和认证（110）的组合。 第二数据分组的加密和认证处理可以在第一数据分组的加密和授权处理完成之前开始。

公开(公告)号：WO01052472A1

公开(公告)日：2001-07-19

申请号：PCT/JP2000/009129

申请日：2000-12-22

IPC: H04L9/06 ,  H04L9/10 ,  H04L9/32

CPC classification number: H04L9/0637 ,  H04L9/0643 ,  H04L2209/125 ,  H04L2209/38

Abstract: In order to encipher data while enciphering other data, a memory (55) is arranged in parallel to a feedback line (65) for feedback to a selector (54) from an enciphering module (51) using an encryption key (K). If an interrupt (IT) for processing plaintext block data (Ni) occurs during the processing of plaintext block data (Mi), the cryptogram block data (Ci) being in process when the interrupt (IT) occurs is stored in a register (56). When the processing of the plaintext block data Ni is completed, a selector (54) selects the cryptogram block data (Ci) stored in the memory (55), and the processing of plaintext block data (Mi+1) is started.

Abstract translation: 为了在对其他数据进行加密的同时对数据进行加密，存储器（55）与反馈线路（65）并行布置，以使用加密密钥（K）从加密模块（51）反馈到选择器（54）。 如果在明文块数据（Mi）的处理期间发生用于处理明文块数据（Ni）的中断（IT），则在中断（IT）发生时正在处理的密码块数据（Ci）被存储在寄存器（56） ）。 当明文块数据Ni的处理完成时，选择器（54）选择存储在存储器（55）中的密码块数据（Ci），开始明文块数据（Mi + 1）的处理。

公开(公告)号：WO0075750A3

公开(公告)日：2001-02-15

申请号：PCT/US0015871

申请日：2000-06-09

Applicant: MICROSOFT CORP

Inventor： VENKATESAN RAMARATHNAM ,  JAKUBOWSKI MARIUSZ

IPC: G09C1/00 ,  H04L9/32 ,  H04K1/00

CPC classification number: H04L9/0643 ,  H04L2209/125 ,  H04L2209/38

Abstract: A technique which implements a primitive for computing, e.g., checksum, this primitive replaces a mod(M) operation with a series of simple elementary register operations (20). These operations include mod 2 multiplications, order manipulations (e.g., byte or word swaps), and additions - all of which are extremely simple to implement and require very few processing cycles to execute. Hence, use of our inventive technique can significantly reduce the processing time to compute various cryptographic parameters, such as, e.g., a message authentication code (MAC) (400), or to implement a stream cipher (23) over that conventionally required. This technique has both invertible and non-invertible variants.

Abstract translation: 实现用于计算例如校验和的原语的技术，该原语用一系列简单的基本寄存器操作（20）代替mod（M）操作。 这些操作包括mod 2 n乘法，顺序处理（例如，字节或字交换）和添加 - 所有这些都是非常简单的实现，并且需要很少的处理周期来执行。 因此，使用本发明的技术可以显着减少计算各种加密参数（例如消息认证码（MAC）（400））的处理时间，或者实现传统上所需的流密码（23）。 这种技术具有可逆和非可逆变体。

公开(公告)号：WO00019386A1

公开(公告)日：2000-04-06

申请号：PCT/EP1999/007026

申请日：1999-09-21

IPC: G06F21/55 ,  G06F21/72 ,  G06F21/75 ,  G06F21/77 ,  G06K19/07 ,  G06K19/073 ,  G09C1/00 ,  H04L9/06 ,  H04L9/28 ,  G07F7/10 ,  G06F1/00

CPC classification number: H04L9/003 ,  G06F21/72 ,  G06F21/75 ,  G06F21/755 ,  G06F21/77 ,  G06F2207/7219 ,  G06K19/07 ,  G06K19/073 ,  G06K19/07363 ,  H04L2209/08 ,  H04L2209/125

Abstract: The invention relates to a data processing device (100) and to a method for operating the data processing device, notably a chip card. Said device comprises an integrated circuit which in accordance with a clock pulse carries out calculating operations, especially cryptographic operations, data inputs and outputs and data transfers from and to registers of the integrated circuit. To this end the integrated circuit (10) is controlled such that the calculating operations, on the one hand, and the input/output of data and data transfer from register to register or between registers, on the other hand, are carried out time-parallel.

Abstract translation: 本发明涉及一种数据处理装置（100）和用于与集成电路，一种操作数据处理装置，特别是智能卡的方法，其响应于时钟信号的算术运算，在特定的加密操作，数据输入或支出以及来自数据传输或 执行到所述集成电路的寄存器。 在此，该集成电路（10）被控制，使得算术运算的，一方面的执行和数据输入 - / - 从寄存器输出和数据传送到在时间寄存器或寄存器之间，在另一方面，平行。

公开(公告)号：WO9944329A2

公开(公告)日：1999-09-02

申请号：PCT/CA9900176

申请日：1999-02-26

Applicant: MOSAID TECHNOLOGIES INC

Inventor： JONES DAVID E ,  O'CONNELL CORMAC M

IPC: G06F13/36 ,  G06F7/50 ,  G06F7/52 ,  G06F7/72 ,  G09C1/00 ,  H04L9/00 ,  H04L9/06 ,  H04L9/30

CPC classification number: G06F7/5324 ,  G06F7/49931 ,  G06F7/5052 ,  G06F7/72 ,  G06F7/722 ,  G06F2207/382 ,  G06F2207/3828 ,  H04L9/14 ,  H04L2209/125

Abstract: An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

Abstract translation: 加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。 该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。 通过双端口存储器在处理元件之间传送数据。 中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。 通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并在多个周期中循环运行。 乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器，在处理元件和中央处理器之间共享。

公开(公告)号：WO99000783A1

公开(公告)日：1999-01-07

申请号：PCT/JP1998/002915

申请日：1998-06-30

IPC: G09C1/00 ,  H04L9/06

CPC classification number: H04L9/0625 ,  H04L2209/125

Abstract: A ciphering apparatus of common key type, wherein a plurality of rounding units are connected in cascade, the i-th rounding unit is fed with input data Li, Ri, the input data Ri are subjected to nonlinear transformation by a nonlinear function unit depending upon the key data, the exclusive-OR output of the output of the nonlinear function unit and the input data Li is outputted as data Ri+1 to the (i+1)-th rounding unit, and the input data Ri are outputted as data Li+1 to the (i+1)-th rounding unit. The nonlinear function unit includes: a key-dependent linear transforming unit for subjecting the input Ri to key-dependent linear transformation; a dividing unit for dividing the output into four data in0, in1, in2 and in3; first nonlinear transforming units for subjecting the divided data to nonlinear transformation to output data mid00, mid01, mid02 and mid03; a key-dependent linear transforming unit for correlating these transformed outputs to each other and subjecting them to linear transformation based upon the key data to output data mid10, mid11, mid12 and mid13; second nonlinear trasnforming units for subjecting the transformed outputs to nonlinear transformation to output data out0, out1, out2 and out3; and a coupling unit for coupling the transformed outputs to output data Y.

Abstract translation: 一种公共密钥型的加密装置，其中多个舍入单元级联连接，第i个舍入单元馈入输入数据Li，Ri，输入数据Ri由非线性函数单元进行非线性变换，取决于 将关键数据，非线性功能单元的输出的异或输出和输入数据Li作为数据Ri + 1输出到第（i + 1）个舍入单元，输入数据Ri作为数据输出 Li + 1到第（i + 1）个舍入单元。 所述非线性函数单元包括：密钥相关线性变换单元，用于对所述输入Ri进行按键依赖的线性变换; 分割单元，用于将输出分成四个数据in0，in1，in2和in3; 第一非线性变换单元，用于对分割数据进行非线性变换，以输出mid00，mid01，mid02和mid03中的数据; 一个依赖关键的线性变换单元，用于将这些变换的输出相互关联，并使它们基于密钥数据进行线性变换，以在10中，中间11，中间12和中间13输出数据; 用于对经变换的输出进行非线性变换以输出数据out0，out1，out2和out3的第二非线性调制单元; 以及用于将变换的输出耦合到输出数据Y的耦合单元。