公开(公告)号：WO2011134079A8

公开(公告)日：2012-01-12

申请号：PCT/CA2011050136

申请日：2011-03-10

Applicant: MOSAID TECHNOLOGIES INC ,  PYEON HONG BEOM

Inventor： PYEON HONG BEOM

IPC: G11C13/00 ,  G11C7/00 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C13/0028 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/72

Abstract: A phase change memory is disclosed. The phase change memory has a plurality of block units. The block units are alternately selected. The alternate block unit selection suppresses peak current ground bouncing on sub-wordline and connected ground line through sub-wordline driver transistor. An alternate bitline selection avoids adjacent cell heating interference in the selected block unit.

Abstract translation: 公开了一种相变存储器。 相变存储器具有多个块单元。 交替选择块单元。 替代块单元选择抑制子字线上的峰值电流接地跳变，并通过子字线驱动晶体管抑制连接的地线。 替代位线选择避免了所选块单元中的相邻单元加热干扰。

公开(公告)号：WO2011026218A9

公开(公告)日：2011-04-21

申请号：PCT/CA2010001321

申请日：2010-08-27

Applicant: GILLINGHAM PETER B ,  MOSAID TECHNOLOGIES INC

Inventor： GILLINGHAM PETER B

IPC: H01L23/488 ,  G11C5/06 ,  H01L21/71 ,  H01L21/98 ,  H01L23/50 ,  H03K17/56

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/06 ,  H01L21/02697 ,  H01L21/82 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/03 ,  H01L24/16 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/14 ,  H03K17/00 ,  H01L2924/00

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract translation: 在适用于互连IC堆叠的集成电路（IC）中，除了不间断的TSV之外，还提供了中断的通硅通孔（TSV）。 中断的TSV提供除了堆栈的IC之间的公共并行路径之外的信号路径。 这允许使用TSV实现IC识别方案和其他功能，而不需要堆叠的替代IC的角旋转。

公开(公告)号：WO2009079752A8

公开(公告)日：2010-01-14

申请号：PCT/CA2008002180

申请日：2008-12-11

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI

Inventor： KIM JIN-KI

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：WO2009088574A9

公开(公告)日：2009-10-08

申请号：PCT/US2008084869

申请日：2008-11-26

Applicant: MOSAID TECHNOLOGIES INC ,  PRZYBYLSKI STEVEN A

Inventor： PRZYBYLSKI STEVEN A

IPC: H04L12/42 ,  G06F13/42

CPC classification number: H04L12/4637 ,  G06F13/4243 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

Abstract translation: 在集群环网络拓扑中，并行访问从属设备组，使得环周围的等待时间与集群的数量成正比，并且不与集成电路的数量成比例。 群集的设备共享输入和输出环段，使得到达输入段的数据包能够被群集中的所有设备接收和解释。 在其他实施例中，每个群集中没有一个，一些或所有但是一个从属装置都睡着或以其他方式被禁用，使得它们不输入和解释传入分组。 无论如何，在所有实施例中，集群的从属装置可能在控制器的指导下协作以确保其中至多有一个主动地在任何给定时间主动驱动输出区段。 设备可以通过设备ID，集群ID或其组合来寻址。 本发明的实施例适于利用多芯片模块实现和垂直电路堆叠的形式。

公开(公告)号：WO2009097681A1

公开(公告)日：2009-08-13

申请号：PCT/CA2009000130

申请日：2009-02-03

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI

Inventor： KIM JIN-KI

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08

CPC classification number: G11C16/08 ,  G06F12/0246 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/22

Abstract: A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.

Abstract translation: 具有至少两个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小和核心控制器。 核心控制器是每个银行本地的，并且管理银行的存储器访问操作，包括读取，编程和擦除操作。 每个核心控制器控制行电路，列电路，电压发生器和本地输入/输出路径电路的定时和激活，用于存储体的相应存储器存取操作。 并发操作可在多个银行中执行，以提高性能。 每个银行的页面大小可配置页面大小的配置数据，以便仅响应于地址数据激活所选择的字线。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。

公开(公告)号：WO2007036050B1

公开(公告)日：2007-05-24

申请号：PCT/CA2006001609

申请日：2006-09-29

Applicant: MOSAID TECHNOLOGIES INC ,  OH HAKJUNE ,  PYEON HONG BEOM ,  KIM JIN-KI

Inventor： OH HAKJUNE ,  PYEON HONG BEOM ,  KIM JIN-KI

IPC: G11C11/4197 ,  G11C11/4063 ,  G11C11/4093 ,  G11C16/26

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制到半导体存储器中的串行数据链路接口的输出端口的数据传输的设备，系统和方法。 在一个示例中，闪存设备可具有多个串行数据链路，多个存储体和控制输入端口，这些端口使得存储设备能够将串行数据传输到存储设备的串行数据输出端口。 在另一个示例中，闪存设备可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：WO2004044920A3

公开(公告)日：2004-07-29

申请号：PCT/CA0301733

申请日：2003-11-12

Applicant: MOSAID TECHNOLOGIES INC

Inventor： ROTH ALAN ,  MCKENZIE ROBERT ,  BECCA OSWALD

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array (100) is disclosed. A normal CAM search operation is executed to find the first word segment (102) of a wide word. Once found, a search and delete operation is executed to find all successive word segments (102) of the wide word, with the last word segment (102) being marked as a deleted word segment (102), along a first CAM array direction. Once the last word segment (102) is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment (102). A purge operation is then executed along the opposite CAM array (100) direction to delete all the word segments (102) of the deleted wide word. Match processing circuits (104) in each row of the CAM array (100) can pass search results to an adjacent row (102) above or below it to ensure that only word segments (102) belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract translation: 公开了一种用于搜索和删除CAM阵列（100）中的分段宽字条目的系统和方法。 执行正常的CAM搜索操作以找到宽字的第一字段（102）。 一旦找到，执行搜索和删除操作，以沿着第一CAM阵列方向找到宽字的所有连续字段（102），其中最后字段（102）被标记为删除字段（102）。 一旦最后一个字段（102）被删除，则宽字被认为已被删除，因为后续搜索宽字不会找到其最后一个字段（102）。 然后沿相反的CAM阵列（100）方向执行清除操作，以删除所删除的宽字的所有字段（102）。 CAM阵列（100）的每行中的匹配处理电路（104）可以将搜索结果传递到其上方或下方的相邻行（102），以确保仅搜索属于宽字的字段（102） 并删除操作并在清除操作中删除。

公开(公告)号：WO2004030305A3

公开(公告)日：2004-07-15

申请号：PCT/CA0301390

申请日：2003-09-10

Applicant: MOSAID TECHNOLOGIES INC ,  BROWN DAVID A ,  GILLINGHAM PETER B

Inventor： BROWN DAVID A ,  GILLINGHAM PETER B

IPC: H04L12/56

CPC classification number: H04L45/00 ,  H04L45/7457

Abstract: A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.

Abstract translation: 公开了一种用于搜索密钥的最长前缀匹配的查找表。 查找表提供了单个搜索周期中的键的匹配。 通过将每个匹配存储在查找表中的一个位置来最大化存储在查找表中的匹配数。 二叉树被分成多个级别，每个级别具有多个子树。 为子树存储的子树描述符包含子树中每个节点的字段。 该字段的状态指示节点的条目是否存储在表中。 位向量允许为密钥存储的单个匹配索引。

公开(公告)号：WO03060918A3

公开(公告)日：2003-09-18

申请号：PCT/CA0202026

申请日：2002-12-27

Applicant: MOSAID TECHNOLOGIES INC

Inventor： VLASENKO PETER ,  PERRY DOUGLAS

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/06

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sens node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison. Reference matchlines are used to generate timed control signals for enabling the latch circuits.

Abstract translation: 公开了用于检测CAM阵列的匹配线上的电流的匹配线感测电路。 为了实现更高的感测速度和改善的感测余量，将匹配线与感测电路感测节点分离。 更具体地说，匹配线感测电路感测节点接收参考电流，该参考电流足够高以将感测节点维持在高逻辑电平。 该参考电流由与存储单元下拉路径相同的虚拟下拉路径生成，以确保参考电流随着存储单元电流的变化而跟踪。 最初在地电位的匹配线经过加速预充电直到低于VDD的预设电压电平，以克服尾部寄生电流并最小化匹配线的电压摆动以节省电力。 在感测期间，匹配电流与参考电流进行比较，并且连接到感测节点的锁存电路提供指示比较结果的全CMOS输出信号。 参考匹配线用于产生用于启用锁存电路的定时控制信号。

公开(公告)号：WO2003065657A1

公开(公告)日：2003-08-07

申请号：PCT/CA2003/000138

申请日：2003-01-30

Applicant: MOSAID TECHNOLOGIES, INC. ,  WYATT, Richard, M.

Inventor： WYATT, Richard, M.

IPC: H04L12/56

CPC classification number: H04L45/74 ,  H04L45/745 ,  H04L45/7453 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13167

Abstract: A multistage switch includes a matrix of coupled switch devices. A logical link comprising a plurality of physical links couples a destination through the plurality of physical links to a plurality of ports in the multistage switch. Each switch device performs trunk aware forwarding to reduce the forwarding of received frames through the matrix of coupled switch devices to the destination in order to reduce unnecessary traffic in the multistage switch.

Abstract translation: 多级开关包括耦合开关器件的矩阵。 包括多个物理链路的逻辑链路通过多个物理链路将目的地耦合到多级交换机中的多个端口。 每个交换机设备执行中继线转发，以减少通过耦合的交换设备矩阵将接收的帧转发到目的地，以便减少多级交换机中的不必要的业务。