公开(公告)号：WO2005059930A3

公开(公告)日：2006-03-09

申请号：PCT/US2004041758

申请日：2004-12-14

Applicant: MOTOROLA INC ,  CROSWELL ROBERT T ,  DUNN GREGORY J ,  LEMPKOWSKI ROBERT B ,  TUNGARE AROON V ,  SAVIC JOVICA

Inventor： CROSWELL ROBERT T ,  DUNN GREGORY J ,  LEMPKOWSKI ROBERT B ,  TUNGARE AROON V ,  SAVIC JOVICA

IPC: H01G20060101 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06 ,  H01G4/20

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm

Abstract translation: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm

公开(公告)号：WO2005065274A3

公开(公告)日：2005-07-21

申请号：PCT/US2004/043421

申请日：2004-12-22

Applicant: MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE ,  DUNN, Gregory J., ,  PETSINGER, Jeffrey M., ,  SAVIC, Jovica,

Inventor： DUNN, Gregory J., ,  PETSINGER, Jeffrey M., ,  SAVIC, Jovica,

IPC: H01Q1/38

Abstract: A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

公开(公告)号：WO2005059930A2

公开(公告)日：2005-06-30

申请号：PCT/US2004/041758

申请日：2004-12-14

Applicant: MOTOROLA, INC. ,  CROSWELL, Robert T. ,  DUNN, Gregory J. ,  LEMPKOWSKI, Robert B. ,  TUNGARE, Aroon V. ,  SAVIC, Jovica

Inventor： CROSWELL, Robert T. ,  DUNN, Gregory J. ,  LEMPKOWSKI, Robert B. ,  TUNGARE, Aroon V. ,  SAVIC, Jovica

IPC: H01G

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm 2 . The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract translation: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

公开(公告)号：WO2007106642A2

公开(公告)日：2007-09-20

申请号：PCT/US2007/062376

申请日：2007-02-19

Applicant: MOTOROLA, INC. ,  SAVIC, Jovica, ,  CHELINI, Remy J., ,  DUNN, Gregory J.,

Inventor： SAVIC, Jovica, ,  CHELINI, Remy J., ,  DUNN, Gregory J.,

IPC: H01G7/00 ,  H01K3/10

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2203/025 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract translation: 公开了一种在印刷电路板上形成嵌入式电容器的方法。 通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。 另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。 在第二电介质层的顶部形成第三电极。 通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。

公开(公告)号：WO2007075713A2

公开(公告)日：2007-07-05

申请号：PCT/US2006/048471

申请日：2006-12-19

Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  CROSWELL, Robert, T. ,  KUMPF, George, H. ,  SVIGELJ, John, A.

Inventor： DUNN, Gregory, J. ,  CROSWELL, Robert, T. ,  KUMPF, George, H. ,  SVIGELJ, John, A.

IPC: H01Q15/24

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）电耦合在两个导电板（318）之间的至少一个电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）和（b）嵌入印刷电路板（302）内的夹层电容器中的至少一个。

公开(公告)号：WO2006130244A3

公开(公告)日：2006-12-07

申请号：PCT/US2006/013995

申请日：2006-04-14

Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  DEAN, Timothy, B.

Inventor： DUNN, Gregory, J. ,  CHELINI, Remy, J. ,  DEAN, Timothy, B.

IPC: B21C37/02 ,  B05D5/12

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

公开(公告)号：WO2005062803A3

公开(公告)日：2006-02-16

申请号：PCT/US2004042529

申请日：2004-12-17

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  DEAN TIMOTHY B ,  GAMBOA CLAUDIA V ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  DEAN TIMOTHY B ,  GAMBOA CLAUDIA V ,  SAVIC JOVICA

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/42 ,  B32B9/00

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (> 1000 pf/mm²).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器。

公开(公告)号：WO2005065274A2

公开(公告)日：2005-07-21

申请号：PCT/US2004043421

申请日：2004-12-22

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  PETSINGER JEFFREY M ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  PETSINGER JEFFREY M ,  SAVIC JOVICA

IPC: H01Q1/38 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K3/0023 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/064 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0571

Abstract: A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

Abstract translation: 电介质片（500,600,1621）包括可以玻璃增强的光电介质支撑层（505,1630）和电介质层压板（510,605）。 介电层压板包括设置在第一和第二金属箔层之间的第一和第二金属箔层（415,660; 210,665,1605,1610）以及介电层（405,655,1620）。 第一金属箔层粘附到光电介质支撑层。 在包括电介质片的印刷电路和贴片天线中，通过根据电路图案去除金属来图案化第一金属层，并且通过根据电路图案去除电介质材料来图案化光电介质支撑层。

公开(公告)号：WO2005035240A1

公开(公告)日：2005-04-21

申请号：PCT/US2004/033315

申请日：2004-10-08

Applicant: MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE ,  DEAN, Timothy B.,? ,  DUNN, Gregory J.,? ,  CHELINI, Remy J.,? ,  GAMBOA, Claudia, V.,?

Inventor： DEAN, Timothy B.,? ,  DUNN, Gregory J.,? ,  CHELINI, Remy J.,? ,  GAMBOA, Claudia, V.,?

IPC: B32B15/20

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract translation: 在一个实施例中，可剥离电路板箔（200）具有通过无机剥离材料（215）粘合的金属支撑层（205）和导电金属箔层（210）。 导电金属箔层具有涂覆有高温抗氧化剂屏障（220）并具有小于0.05微米RMS的粗糙度的暴露表面（212）。 在第二实施例中，可剥离印刷电路箔（200）具有设置在导电金属箔层的暴露表面上的结晶的电介质氧化物层（405）和设置在结晶的电介质氧化物层上的电极层（415），形成 可以粘附到柔性或刚性电路板的层的介电可剥离电路板箔（400），之后金属支撑层可以被剥离，留下包括金属箔层，结晶化电介质氧化物层， 和电极层。

公开(公告)号：WO2004109719A3

公开(公告)日：2005-04-21

申请号：PCT/US2004014665

申请日：2004-05-11

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

IPC: H01C7/00 ,  H01C17/065 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K3/12 ,  H01C1/012

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

Abstract: A printed circuit polymer thick film (PTF) resistor (410, 420) includes tolerance control material (425, 426, 440) that substantially surrounds the resistor body (423) and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment (420), the tolerance control material is the same metallic material as the printed circuit conductors (430), and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad (435) of the resistor. A layout cell (700) is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

Abstract translation: 印刷电路聚合物厚膜（PTF）电阻器（410,420）包括基本上围绕电阻体（423）的公差控制材料（425,426,440），并显着地改善了电阻与电阻器长度的线性度，并显着地降低 电阻 - 电阻和板对板制造差异。 在一个实施例（420）中，公差控制材料是与印刷电路导体（430）相同的金属材料，并且形成在电阻器主体的每一侧上的两个指形图案中，每个指形图案连接到一个端子焊盘（435 ）的电阻。 布局单元（700）用于制造PTF电阻。 一种制造PTF电阻的方法。