公开(公告)号：WO2019204119A1

公开(公告)日：2019-10-24

申请号：PCT/US2019/027005

申请日：2019-04-11

Applicant: SUNPOWER CORPORATION

Inventor： LIN, Yafu ,  JACOB, David

IPC: H01L31/18 ,  H01L31/02 ,  H01L31/0236 ,  H01L31/036

Abstract: Methods of fabricating solar cells having junctions retracted from cleaved edges, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface, a back surface, and sidewalls. An emitter region is in the substrate at the light-receiving surface of the substrate. The emitter region has sidewalls laterally retracted from the sidewalls of the substrate. A passivation layer is on the sidewalls of the emitter region.

公开(公告)号：WO2019190453A1

公开(公告)日：2019-10-03

申请号：PCT/US2018/024294

申请日：2018-03-26

Applicant: INTEL CORPORATION ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  TAN, Cen ,  KRYSAK, Marie

Inventor： BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  TAN, Cen ,  KRYSAK, Marie

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication, and the resulting devices, are described. In an example, method of dry etching a film includes forming a transition metal oxide film having a latent pore-forming material therein. The method also includes removing a surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also includes removing the porous region of the transition metal oxide film.

公开(公告)号：WO2019055052A1

公开(公告)日：2019-03-21

申请号：PCT/US2017/052109

申请日：2017-09-18

Applicant: INTEL CORPORATION ,  GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

Inventor： GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

IPC: H01L45/00

Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

公开(公告)号：WO2019055003A1

公开(公告)日：2019-03-21

申请号：PCT/US2017/051367

申请日：2017-09-13

Applicant: INTEL CORPORATION ,  MAJHI, Prashant ,  PILLARISETTY, Ravi ,  KARPOV, Elijah V. ,  DOYLE, Brian S. ,  SHARMA, Abhishek A.

Inventor： MAJHI, Prashant ,  PILLARISETTY, Ravi ,  KARPOV, Elijah V. ,  DOYLE, Brian S. ,  SHARMA, Abhishek A.

IPC: H01L45/00 ,  H01L43/02

CPC classification number: H01L27/2409 ,  H01L27/224 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：WO2019005167A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040510

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

Inventor： STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, where the intermediate layer includes oxygen. A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.

公开(公告)号：WO2019005156A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040493

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

Inventor： O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has an uppermost is 10-20 times larger than the MTJ device. The MTJ device includes a free layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the free layer and a fixed layer disposed on the tunnel barrier.

公开(公告)号：WO2019005114A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040328

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  MA, Sean T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  METZ, Matthew V. ,  HUANG, Cheng-Ying ,  KENNEL, Harold W. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

Inventor： MA, Sean T.

IPC: H01L29/78 ,  H01L29/66

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：WO2019005020A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/039597

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： EID, Feras ,  ALEKSOV, Aleksandar ,  DOGIAMIS, Georgios C. ,  SOUNART, Thomas L. ,  SWAN, Johanna

IPC: H01L23/58 ,  H01L23/14 ,  H01L23/485 ,  H01L49/02 ,  H01L41/08

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a piezoelectrically actuated tunable capacitor having a variable capacitance formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. A piezoelectric actuator of the tunable capacitor includes first and second conductive electrodes and a piezoelectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：WO2018236357A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038383

申请日：2017-06-20

Applicant: INTEL CORPORATION ,  MAJHI, Prashant ,  DOYLE, Brian S. ,  SHARMA, Abhishek A. ,  KARPOV, Elijah V. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  AHMED, Khaled

Inventor： MAJHI, Prashant ,  DOYLE, Brian S. ,  SHARMA, Abhishek A. ,  KARPOV, Elijah V. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  AHMED, Khaled

IPC: H01L29/786 ,  H01L29/78 ,  H01L21/768 ,  H01L29/423

Abstract: Thin film transistors having relatively increased width are described. In an example, an integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A semiconducting oxide material is on the insulator structure. The semiconducting oxide material is conformal with the topography of the insulator structure. A gate electrode is over a first portion of the semiconducting oxide material on the insulator structure. The gate electrode has a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode. A second conductive contact is adjacent the second side of the gate electrode.

公开(公告)号：WO2018236354A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038379

申请日：2017-06-20

Applicant: INTEL CORPORATION ,  LIN, Kevin ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  KABIR, Nafees A. ,  VREELAND, Richard F.

Inventor： LIN, Kevin ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  KABIR, Nafees A. ,  VREELAND, Richard F.

IPC: H01L21/768

Abstract: Metal spacer-based approaches for conductive interconnect and via fabrication is described. In an example, an integrated circuit structure includes a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) structure above a substrate. Each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD structure. The ILD structure includes a plurality of first and second ILD lines alternating with the alternating first and second conductive lines. A first hardmask component is on and aligned with the first conductive lines. A second hardmask component is on an aligned with the second conductive lines. A conductive via is in an opening in the first hardmask component and on one of the first conductive lines.