公开(公告)号：WO2018236354A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038379

申请日：2017-06-20

Applicant: INTEL CORPORATION ,  LIN, Kevin ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  KABIR, Nafees A. ,  VREELAND, Richard F.

Inventor： LIN, Kevin ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  KABIR, Nafees A. ,  VREELAND, Richard F.

IPC: H01L21/768

Abstract: Metal spacer-based approaches for conductive interconnect and via fabrication is described. In an example, an integrated circuit structure includes a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) structure above a substrate. Each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD structure. The ILD structure includes a plurality of first and second ILD lines alternating with the alternating first and second conductive lines. A first hardmask component is on and aligned with the first conductive lines. A second hardmask component is on an aligned with the second conductive lines. A conductive via is in an opening in the first hardmask component and on one of the first conductive lines.

公开(公告)号：WO2014209327A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048307

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  HOURANI, Rami ,  HAN, Eungnak ,  BLACKWELL, James M.

Inventor： BRISTOL, Robert L. ,  HOURANI, Rami ,  HAN, Eungnak ,  BLACKWELL, James M.

IPC: H01L21/027 ,  H01L21/28

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基板的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：WO2014116496A1

公开(公告)日：2014-07-31

申请号：PCT/US2014/011856

申请日：2014-01-16

Applicant: INTEL CORPORATION ,  KOBRINSKY, Mauro J. ,  BRISTOL, Robert L. ,  MAYBERRY, Michael C.

Inventor： KOBRINSKY, Mauro J. ,  BRISTOL, Robert L. ,  MAYBERRY, Michael C.

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/0337 ,  H01L27/224 ,  H01L28/82

Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

Abstract translation: 公开了用于提供具有大体波形轮廓的MIM电容器的技术和结构。 使用牺牲性自组织材料提供波纹形状，其有效地产生响应于被形成MIM电容器的介电材料的处理（热或其它合适的刺激）的图案。 自组织材料可以是例如响应于热或其它刺激而分离成两个交替相的定向自组装材料层，其中相中的一个相可以相对于另一相被选择性地蚀刻到 提供所需的图案。 在另一个例子中，自组织材料是在加热时聚结成孤岛的材料层。 根据本公开将会理解，所公开的技术可以用于例如增加每单位面积的电容，其可以通过蚀刻更深的电容器沟槽/孔来缩放。

公开(公告)号：WO2015147843A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032073

申请日：2014-03-27

Applicant: INTEL CORPORATION ,  BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

Inventor： BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

IPC: C23C16/455 ,  C23C16/52 ,  H01L21/285

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

公开(公告)号：WO2015047345A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062456

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

IPC: H01L21/31

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：WO2015047318A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062319

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  GSTREIN, Florian ,  SCHENKER, Richard E. ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  YOO, Hui Jae

Inventor： BRISTOL, Robert L. ,  GSTREIN, Florian ,  SCHENKER, Richard E. ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  YOO, Hui Jae

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

Abstract translation: 描述了用于后端（BEOL）互连的消减自对准通孔和插塞图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 互连结构还包括设置在互连结构的第一层上方的互连结构的第二层。 第二层包括在垂直于第一方向的第二方向上交替的金属线和介质线的第二光栅。 介质线具有低于金属线的最下表面的最下表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一光栅的金属线与第二光栅的金属线间隔开。

公开(公告)号：WO2018118092A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068586

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian ,  BLACKWELL, James M. ,  KRYSAK, Marie ,  CHANDHOK, Manish ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  WARD, Curtis W. ,  SIVAKUMAR, Swaminathan ,  TAN, Elliot N.

Inventor： SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian ,  BLACKWELL, James M. ,  KRYSAK, Marie ,  CHANDHOK, Manish ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  WARD, Curtis W. ,  SIVAKUMAR, Swaminathan ,  TAN, Elliot N.

IPC: H01L21/768 ,  H01L21/027

Abstract: Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：WO2018118091A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068584

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  BRISTOL, Robert L. ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

Inventor： CHAWLA, Jasmeet S. ,  MANIPATRUNI, Sasikanth ,  BRISTOL, Robert L. ,  LIN, Chia-Ching ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：WO2018101961A1

公开(公告)日：2018-06-07

申请号：PCT/US2016/064684

申请日：2016-12-02

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  LIN, Kevin L. ,  BLACKWELL, James M.

Inventor： BRISTOL, Robert L. ,  LIN, Kevin L. ,  BLACKWELL, James M.

IPC: H01L21/768 ,  H01L21/027

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above the plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

公开(公告)号：WO2016209205A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/036984

申请日：2015-06-22

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  BLACKWELL, James M. ,  HOURANI, Rami

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  HOURANI, Rami

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/76816 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0335 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76897 ,  H01L2224/16225

Abstract: Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.

Abstract translation: 描述了使用用于后端（BEOL）互连的自底向上交联的电介质的图像色调反转。 在一个示例中，包括金属化层的半导体结构包括在衬底上方的层间电介质（ILD）层中的多个沟槽。 预催化剂层位于多个沟槽中的一个或多个但不是全部的侧壁上。 电介质材料的交联部分在多个沟槽中的一个或多个中靠近预催化剂层。 导电结构在其余的沟槽中。