公开(公告)号：WO1989010029A1

公开(公告)日：1989-10-19

申请号：PCT/US1989001050

申请日：1989-03-14

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  WENG, Lih-Jyh

IPC: H03M13/00

CPC classification number: H03M13/1515 ,  G11B20/1813 ,  G11B20/1883 ,  G11B2220/20 ,  H03M13/29 ,  H03M13/2903 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/3738

Abstract: A method for encoding information in a codeword which may be subjected to no more than a predetermined degree of corruption, and then, without fully decoding a corrupted version of the codeword, determining from the corrupted codeword whether the information was used in encoding the codeword; the information is encoded as a first preliminary code sequence in accordance with a first code; the codeword is formed by combining the first preliminary code sequence with a second preliminary code sequence generated in accordance with a second code; the first preliminary code sequence is stripped from the corrupted version of the code word to derive a test sequence comprising a corrupted version of possibly the second preliminary code sequence; the test sequence is decoded in accordance with the second code; and a determination is made, based on the decoding, whether the information was used in encoding the codeword. In another aspect, bad sector, servo correction, and sector address values are encoded for storage in a header associated with a sector of storage on a storage medium by encoding the address value with leading zero symbols in accordance with a code having a first rate, encoding the bad sector and servo correction values in a systematic code having a second rate, and combining the first and second preliminary code sequences to generate a codeword of the first code such that the bad sector and servo correction values appear explicitly in the codeword but the sector address value does not appear explicitly in the codeword.

Abstract translation: 一种对码字中的信息进行编码的方法，所述方法可以经历不超过预定程度的损坏，然后，在不完全解码所述码字的损坏版本的情况下，从所述损坏的码字确定所述信息是否用于编码所述码字; 该信息根据第一代码被编码为第一初步代码序列; 通过组合第一初步码序列与根据第二码产生的第二初步码序列形成码字; 从代码字的损坏版本剥离第一初步代码序列以导出包括可能的第二初步代码序列的损坏版本的测试序列; 测试序列根据第二代码进行解码; 并且基于解码进行该信息是否用于编码码字的确定。 在另一方面，通过根据具有第一速率的代码对具有前导零符号的地址值进行编码，将坏扇区，伺服校正和扇区地址值编码为用于存储在与存储介质上的存储扇区相关联的报头中， 在具有第二速率的系统代码中对坏扇区和伺服校正值进行编码，并且组合第一和第二初步码序列以产生第一码的码字，使得坏扇区和伺服校正值明显地出现在码字中，但是 扇区地址值没有明确地出现在码字中。

公开(公告)号：WO1989009442A1

公开(公告)日：1989-10-05

申请号：PCT/US1989001311

申请日：1989-03-30

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  RAMANUJAN, Raj, Kannan ,  BANNON, Peter, Joseph ,  STEELY, Simon, Carl, Jr.

IPC: G06F09/34

CPC classification number: G06F9/3812 ,  G06F9/3861

Abstract: A method and apparatus optimize the performance of a multiple cache system computer (Fig. 1) having separate caches for data (60) and instructions (50) in which all writes to the data cache are monitored. If an address tag of the item being written matches one of a list of tags (110) representing valid instructions currently stored in the instruction cache (50), a flag (120) called I-FLUSH-ON-REI is set. Until this flag (120) is set, REI (Return from Exception or Interrupt) instruction will not flush the instruction cache (50). When the flag (120) is set, an REI command will also flush or clear the instruction cache (50). Thus, the instruction cache (50) is only flushed when an address referenced by an instruction is modified, so as to reduce the number of times the cache is flushed and optimize the computer's speed of operation.

Abstract translation: 一种方法和装置优化具有用于数据（60）和指令（50）的单独高速缓存的多高速缓存系统计算机（图1）的性能，其中监视对数据高速缓存的所有写入。 如果要写入的项目的地址标签匹配表示当前存储在指令高速缓存（50）中的有效指令的标签列表（110）中的一个，则设置称为I-FLUSH-ON-REI的标志（120）。 在设置该标志（120）之前，REI（从异常返回）指令不会刷新指令高速缓存（50）。 当标志（120）被置位时，REI命令也将刷新或清除指令高速缓冲存储器（50）。 因此，当指令引用的地址被修改时，仅刷新指令高速缓冲存储器（50），以便减少缓存刷新的次数并优化计算机的操作速度。

公开(公告)号：WO1989007826A1

公开(公告)日：1989-08-24

申请号：PCT/US1989000576

申请日：1989-02-13

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  HASHEMI, A., David ,  REINSCHMIDT, Robert, M.

IPC: G11C01/34

CPC classification number: G11C11/416

Abstract: A bipolar random access memory (30) having no write recovery time. During a data write operation, while the memory state of the memory cell (36) is being shifted, a data bypass circuit (38) sets a sense latch (72) in the sense amplifier (32) to store the new state to which the memory cell (36) is being set. To prevent the sense latch (72) from being shifted by transient write recovery currents charging bit line parasitic capacitances (86 and 87) following the data write operation, a read/write transmission circuit (34) isolates the sense amplifier (32) from the bit lines (41 and 42), diverts current from the sense amplifier (32) to a source of high voltage to charge the parasitic capacitance (86 and 87), and then realigns the sense amplifier (32) to the bit lines (41 and 42).

公开(公告)号：WO1989003112A1

公开(公告)日：1989-04-06

申请号：PCT/US1988003453

申请日：1988-10-01

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MALLARY, Michael, L.

IPC: G11B05/66

CPC classification number: G11B5/66

Abstract: The magnetic medium includes a soft magnetic layer separated from the hard magnetic recording layer by a nonmagnetic buffer layer. Virtual magnetic images induced in the soft magnetic layer reduce off-track magnetization seen by the recording head. Thus, interference caused by tracks adjacent to the track being read is reduced.

Abstract translation: 磁介质包括通过非磁性缓冲层与硬磁记录层分离的软磁性层。 在软磁层中感应的虚拟磁图像减少由记录头看到的偏磁磁化。 因此，减少了与被读取的轨道相邻的轨道引起的干扰。

公开(公告)号：WO1989002130A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002810

申请日：1988-08-16

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  FOSSUM, Tryggve ,  MANLEY, Dwight, P. ,  McKEEN, Francis, X. ,  TEHRANIAN, Michael, M.

IPC: G06F15/347

CPC classification number: G06F9/30141 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F15/8084 ,  G11C8/16

Abstract: A vector register file (35) includes a plurality of read ports (51-55) and write ports (41-43). A control logic (60) is coupled to the vector register file (35) for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from a logical vector register circuit accessed as a first number of register subarrays (99) into a second number of memory banks (500-515) is provided to minimize the vector register access conflicts.

公开(公告)号：WO1989002127A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002955

申请日：1988-09-01

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  TRIOLO, Victoria, M. ,  BLOOM, ELbert ,  HARTWELL, David, W.

IPC: G06F13/40

CPC classification number: G06F5/06 ,  G06F13/405 ,  G06F13/4226

Abstract: A bus adapter connecting a high-speed pended bus (25) to a slower speed non-pended bus (45) includes a first module (69) functioning as a node of the pended bus and a second module (61) functioning as a node of the non-pended bus. An interconnect bus (611) extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

公开(公告)号：WO1989001842A1

公开(公告)日：1989-03-09

申请号：PCT/US1988003003

申请日：1988-09-02

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  SANKAR, Nott, G. ,  PILEEKI, Victor, T. ,  ZAHAYKEVICH, George, A.

IPC: B23K26/00

CPC classification number: B23K26/0613 ,  B23K26/0604 ,  B23K26/382 ,  B23K26/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  B23K2103/52 ,  H05K3/0038 ,  H05K2203/108

Abstract: An apparatus and method for drilling holes in printed wiring boards formed of a plurality materials wherein two or more laser beams are combined along a common path and preferably focussed on the desired drilling site. The wavelengths of the lasers are selected such that they are each rapidly absorbed and therefor vaporized at least one of said materials. The laser beams are preferably focussed by a beam combining mirror. The lasers can be controlled to provide simultaneous or sequential emission of the laser beams.

公开(公告)号：WO1988009011A1

公开(公告)日：1988-11-17

申请号：PCT/US1988001595

申请日：1988-05-13

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  WENG, Lih-Jyh

IPC: G06F11/10

CPC classification number: H03M13/151

Abstract: Error locations and error values are simultaneously found by inserting a first value of x, xa1 (22) into the expressions delta even(x) (24c) and delta odd(x) (24b) and also into an error value polynomial PHI (x) (24a). Next, while the error locator equation is evaluated at the calculated values of delta even(xa1) and delta odd(xa1) to determine if xa1 is a solution (26b), the now known values of the error evaluator polynomial PHI (xa1) and the expression delta odd(xa1) are substituted into an error value formula (26a). Thus as soon as an error location is found, the error can then be quickly corrected (30). Next, the values are calculated for another value of x, xa2 (34b). The newly evaluated expressions are then substituted into the error locator equation and the error value equation formula to determine if xa2 is a solution. If xa2 is a solution, the error value va2 which was simultaneously calculated for xa2 is used to correct the error (20). If xa2 is not a solution, the calculated error value is ignored (28). Then, the expressions are similarly evaluated at the other values of x.

Abstract translation: 通过将x，xa1（22）的第一个值插入表达式delta even（x）（24c）和delta odd（x）（24b）中并将其插入到错误值多项式PHI（x）中同时找到错误位置和错误值 ）（24a）。 接下来，当以计算的delta even（xa1）和delta odd（xa1）的值来评估误差定位器方程，以确定xa1是否是解（26b）时，现在已知的误差估计器多项式PHI（xa1）和 将表达式delta odd（xa1）代入误差值公式（26a）。 因此，一旦发现错误位置，则可以快速校正错误（30）。 接下来，针对x，xa2（34b）的另一个值计算值。 然后将新评估的表达式代入误差定位器方程和误差值方程式，以确定xa2是否为解。 如果xa2是解，则使用同时计算xa2的误差值va2来校正误差（20）。 如果xa2不是解，计算出的误差值被忽略（28）。 然后，在x的其他值上类似地评估表达式。

公开(公告)号：WO1988009010A1

公开(公告)日：1988-11-17

申请号：PCT/US1988001486

申请日：1988-05-06

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  WENG, Lih-Jyh

IPC: G06F11/10

CPC classification number: H03M13/15

Abstract: An encoder (10) encodes a sector of data to produce ECC symbols (28) using a GF(28) code by first appending one or more pseudo data bytes to the sector data bytes. The data string of sector data bytes and pseudo data bytes are then encoded (10) to produce a desired number of 10-bit ECC symbols (28). Two selected bits from each ECC symbol are compared (30) to a known bit pattern (39). If the selected bits match the pattern, the bits are truncated and the remaining 8-bit symbols are concatenated with the data string to form a codeword (36). The codeword bytes can later be decoded, and any error correction performed, by appending the bit pattern as necessary. If the selected bits do not match the pattern, the pseudo data bytes are modified (34) such that encoding the data bytes and the modified pseudo data bytes produce 10-bit ECC symbols with the selected bits matching the bit pattern. The selected bits are then truncated and the remaining 8-bit symbols are concatenated with the data string to form the codeword.

公开(公告)号：WO1988008581A1

公开(公告)日：1988-11-03

申请号：PCT/US1988001276

申请日：1988-04-26

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  DARREL, D., Donaldson ,  RICHARD, B., Gillett, Jr. ,  DOUGLAS, D., Williams

IPC: G06F13/40

CPC classification number: G06F13/4072

Abstract: Bus interface apparatus is provided to drive a high speed bus (67) with two nonoverlapping clock signals (C34/C61). The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals (C34, C61).