Abstract:
A synchronization data detecting unit is provided in a communication system for detecting predetermined synchronization data. The synchronization data are sent in a transmission frame in a communication signal of the communication system. The synchronization data include a sequence of identical binary symbols which are transmitted after scrambling. The synchronization detection unit comprises a descrambler (406) for descrambling the received communication and for producing an output data sequence having multi-level signal values. The multi-level signal values of the descrambler output are smoothed in a filter unit (407). The smoothed signal is compared with a predetermined threshold value. If the smoothed signal exceeds the predefined threshold value, a detection of said synchronized data is indicated.
Abstract:
The present invention relates to burst mode digital communication systems where data transmission is preceded by a preamble for acquisition of carrier and clock synchronization using maximum likelihood (ML) principle. The preamble is sampled and the set of samples obtained is processed using the optimization algorithms of the present invention to provide the ML timing estimate. The optimization algorithms in the present invention consist of three parts. The first part deals with isolating the desired optimal estimate from non-optimal extremes satisfying the same necessary condition, and provides the initial conditions for activating the binary search schemes. The second part performs the binary search for the optimal timing estimate that guarantees the convergence. On the basis of the obtained iterative sequence, the last part constructs a more rapidly convergent sequence to obtain the ML symbol timing estimate. Using the obtained symbol timing estimate, the ML carrier phase estimate can be computed explicitly, and synchronization performed.
Abstract:
A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal ((164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.
Abstract:
A method of chip interleaving in direct sequence spread spectrum communications. A binary code sequence is chosen to have a length N = 2 -1 and to be self-orthogonal. A data string (40) of M = QN+1 bits, QN-1 bits, or QN+S bits, where Q is a positive integer and S is an integer between 1 and N that lacks a common factor with N, is multiplied sequentially (44) with the binary code sequence (42) until N chip frames of M chips each are produced. These chip frames are transmitted to a receiver, and recovered in an equally straightforward manner. The integers Q and N are chosen according to transmission conditions.
Abstract:
A method for sampling a data stream (22) includes receiving a segment of the data stream containing a sequence of known data, together with a source-synchronous clock signal (20), and generating a series of trial sampling clocks (60) by applying a corresponding series of different trial delays to the received clock signal The received segment of the data stream is sampled using each of the trial sampling clocks in turn to generate sampled data. The known data are compared to the sampled data to find comparison results for each of the trial sampling clocks. Responsive to the comparison results, a final delay is set, to be applied to the received clock signal so as to generate a final sampling clock for use in sampling the data stream subsequent to the segment.
Abstract:
While continuing data communication through a communication channel, a frame is captured using a synchronous channel of a frequency different from that of the communication channel thereby to smoothly perform inter-satellite diversity and inter-satellite handover. During the period for which no data is communicated by means of a communication burst (31X) through a communication channel, a frame is captured by means of synchronous bursts (21Y, 21Z) through a synchronous channel of a different frequency. Since the synchronous bursts (21Y, 21Z) include synchronous words (23Y to 25Y, 23Z to 25Z), the timings of the synchronous words (23Y to 25Y, 23Z to 25Z) receivable during the period for which no data is communicated are increased. Alternatively, the synchronous bursts (21Y, 21Z) of the channel of the frequency which is determined for both the transmitter and receiver are transmitted/received during the period, and consequently the frame capture is smoothly carried out.
Abstract:
A method of chip interleaving in direct sequence spread spectrum communications. A binary code sequence is chosen to have a length N=2 -1 (14) and to be self-orthogonal. A data string of M=QN+/-1 bits (10 and 12), where Q is a positive integer, is multiplied sequentially with the binary code sequence until N (14) chip frames of M (10 and 12) chips each are produced. These chip frames are transmitted to a receiver, and recovered in an equally straightforward manner. The integers Q and N are chosen according to transmission conditions.
Abstract:
A digital subscriber line communication system does not require the use of a plain old telephone service (POTS) splitter in the resident's home. Digital signal processing techniques are utilized to adapt to varying subscriber line conditions due to POTS telephone equipment. The digital signal processing techniques eliminate the need for a splitter by reducing susceptibility to distortion due to varying subscriber line characteristics. The digital subscriber line modem utilizes quadrature amplitude modulated (QAM) signals and frequency division multiplexing. The digital subscriber line modem includes a control circuit which includes a rapid retrain circuit. The rapid retrain circuit can retrain the digital subscriber line modem in less than 0.5 seconds.
Abstract:
A method for controlling communication of mobile equipment in which the power consumed by the repetition of useless asynchronous reception for establishing synchronization can be reduced. The control unit (5) of a mobile station which is the mobile equipment controls the duration of asynchronous reception stopping time elapsed until asynchronous reception is again started after the asynchronous reception is temporarily stopped for synchronization establishing so that the duration can be extended in accordance with the number of continuous synchronization establishment failures or the time continuously elapsed from a failure, when the synchronization establishment between the mobile station and a base station has continuously failed.