公开(公告)号：WO2016179595A1

公开(公告)日：2016-11-10

申请号：PCT/US2016/031505

申请日：2016-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： DURYEA, Timothy Paul ,  GARG, Vaibhav

IPC: H03M1/12 ,  G01R27/02

CPC classification number: H03M1/0607 ,  H03K19/0005 ,  H03M1/1076 ,  H03M1/122 ,  H03M1/1245 ,  H03M1/44

Abstract: In described examples, a channel selector (110) for use in an analog-to-digital converter (100) has a sampling circuit for converting an analog input (107) to a digital output (108) within a fault tolerance range. The channel selector (110) includes a reception channel (112), a diagnostic channel (114), and an impedance compensator (116). The reception channel (112) receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel (114) receives a diagnostic signal for verifying the digital output (108) of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator (116) is configured to offset a high channel impedance of the reception channel (112) based on the fault tolerance range of the sampling circuit and when the diagnostic channel (114) is selected.

Abstract translation: 在所描述的示例中，用于模数转换器（100）的通道选择器（110）具有用于在容错范围内将模拟输入（107）转换为数字输出（108）的采样电路。 信道选择器（110）包括接收信道（112），诊断信道（114）和阻抗补偿器（116）。 当接收通道（112）被选择用于与采样电路耦合时，接收信号（112）接收用于传送到采样电路的模拟信号。 诊断通道（114）当选择与采样电路耦合时，接收用于验证采样电路的数字输出（108）的诊断信号。 阻抗补偿器（116）被配置为基于采样电路的容错范围和当选择诊断信道（114）时抵消接收信道（112）的高信道阻抗。

公开(公告)号：WO2016118928A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/014631

申请日：2016-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： BERTRAND, Pierre ,  ROH, June, Chul ,  YAO, Jun

IPC: H04L1/16 ,  H04W76/00

CPC classification number: H04L5/0055 ,  H04L1/1607 ,  H04L1/1621 ,  H04L1/1896 ,  H04L5/001 ,  H04L5/14 ,  H04L5/1469 ,  H04L2001/0093 ,  H04L2001/0097

Abstract: In described examples, a method of operating a wireless communication system includes receiving respective downlink transmissions at N second transceivers (RUs) from a first transceiver (100), where N is a positive integer greater than 1. The reception acknowledgement signals by the N second transceivers are combined into a single reception acknowledgement signal and transmitted to the first transceiver (100).

Abstract translation: 在所描述的示例中，操作无线通信系统的方法包括：从第一收发器（100）接收来自N个第二收发器（RU）的各个下行链路传输，其中N是大于1的正整数。接收确认信号为N秒 收发机被组合成单个接收确认信号并被发送到第一收发器（100）。

公开(公告)号：WO2016109811A1

公开(公告)日：2016-07-07

申请号：PCT/US2015/068313

申请日：2015-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： VEERAMREDDI, Srinivas, Venkata

IPC: H02M3/158 ,  H02M3/155

CPC classification number: H02M3/158 ,  H02M2001/0032 ,  H02M2001/008 ,  Y02B70/16

Abstract: In described examples, a power conversion system includes a PFM controller (245), a PWM controller (255), and an auxiliary voltage output stage (270). The PFM controller (245) controls a power output stage (260) in a PFM mode in response to a power stage voltage output generated by the power output stage (260) during a first period of time in which the power output stage (260) is operating in the PFM mode. The PWM controller (255) controls the power output stage (260) in a PWM mode in response to a power stage voltage output generated by the power output stage (260) during a second period of time in which the power output stage (260) is operating in the PWM mode. The auxiliary voltage output stage (270) generates an auxiliary voltage during a third period of time, where the PWM controller (255) controls the auxiliary voltage output stage (270) using the auxiliary voltage during the third period of time.

Abstract translation: 在所述的示例中，功率转换系统包括PFM控制器（245），PWM控制器（255）和辅助电压输出级（270）。 PFM控制器（245）响应于在功率输出级（260）的第一时间段期间由功率输出级（260）产生的功率级电压输出，在PFM模式中控制功率输出级（260） 在PFM模式下运行。 PWM控制器（255）响应于在功率输出级（260）的第二时段期间由功率输出级（260）产生的功率级电压输出，以PWM模式控制功率输出级（260） 工作在PWM模式。 辅助电压输出级270在第三时间段期间产生辅助电压，在第三时间段期间，PWM控制器255在第三时间段内利用辅助电压来控制辅助电压输出级270。

公开(公告)号：WO2016057883A3

公开(公告)日：2016-04-14

申请号：PCT/US2015/054864

申请日：2015-10-09

Applicant: TEXAN INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： J., Divyasree ,  KAMATH, Anant, Shankar

IPC: H03L7/00 ,  H03L7/18

Abstract: In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider (130) that converts fosc to a resistance, generating an FLL feedback voltage (Vfosc) to generate a loop control signal (OSC cntrl) input to the oscillator (110). In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock generator (100) operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

公开(公告)号：WO2016010905A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/040166

申请日：2015-07-13

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： TAM, Kai Yiu ,  KIAEI, Ali ,  HAROUN, Baher S.

IPC: H03K3/02

CPC classification number: H03B5/04 ,  H03B5/24 ,  H03K3/0231 ,  H03K4/023 ,  H03K4/50 ,  H03K4/502 ,  H03K4/94

Abstract: In described examples, a relaxation oscillator (100) reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current (II) and a second current (12), so that after the first current (II) has been input to a first pair of circuits (120, 140) and the second current (12) has been input to a second pair of circuits (130, 140), the second current (12) is input to the first pair of circuits (120, 140), and the first current (II) is input to the second pair of circuits (130, 140).

Abstract translation: 在所述的实施例中，张弛振荡器（100）通过周期性交换第一电流（II）和第二电流（12）来降低低偏移频率下的温度灵敏度和相位噪声，使得在第一电流（II）已被输入到 已经将第一对电路（120,140）和第二电流（12）输入到第二对电路（130,140），第二电流（12）被输入到第一对电路（120,140 ），并且第一电流（II）被输入到第二对电路（130,140）。

公开(公告)号：WO2015171657A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/029313

申请日：2015-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： CHANNABASAPPA, Rakesh, Yaraduyathinahalli ,  PATIL, Shekhar, Dinkar ,  SUVARNA, Rajeev

IPC: G11C7/18 ,  G06F7/76

CPC classification number: G06F5/10 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C8/16

Abstract: In described examples, apparatus (200) includes a controller (270) and logic circuitry (275). The controller (270) is configured to generate multiple single-bit logic values. Each single-bit logic value has one of: (a) a first value indicating that a data packet has been written into a memory (210); and (b) a second value indicating that a data packet has been read from the memory (210). The logic circuitry (275) is configured to serially stack the single-bit logic values. The apparatus (200) could further include a shift memory bank (280) configured to store the single-bit logic values. The logic circuitry (275) can be configured to serially stack the single-bit logic values in the shift memory bank (280). For example, the logic circuitry (275) can be configured to shift the single-bit logic values in the shift memory bank (280) in different directions and insert one single -bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

Abstract translation: 在所描述的示例中，装置（200）包括控制器（270）和逻辑电路（275）。 控制器（270）被配置为生成多个单位逻辑值。 每个单位逻辑值具有以下之一：（a）指示数据分组被写入存储器（210）的第一值; 和（b）指示已经从存储器（210）读取数据分组的第二值。 逻辑电路（275）被配置为串行堆叠单位逻辑值。 装置（200）还可以包括被配置为存储单位逻辑值的移位存储器组（280）。 逻辑电路（275）可以​​被配置为串行地堆叠移位存储体（280）中的单位逻辑值。 例如，逻辑电路（275）可以​​被配置为在不同的方向上移位移位存储体（280）中的单位逻辑值，并且根据是否将不同的一端插入一个单位逻辑值到存储体 一个逻辑值具有第一或第二值。

公开(公告)号：WO2015143438A1

公开(公告)日：2015-09-24

申请号：PCT/US2015/022030

申请日：2015-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： EDWARDS, Henry, Litzmann ,  SALMAN, Akram, A. ,  MAHMUD, Md. Iqbal

IPC: H01L29/73

CPC classification number: H01L27/0259 ,  H01L27/0825 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/732

Abstract: In described examples, a segmented bipolar transistor (100) includes a p-base in a semiconductor surface (106) including at least one p-base finger (140) having a base metal/silicide stack including a base metal line that contacts a silicide layer (159) on the semiconductor surface of the p-base finger (140). An n+ buried layer (126) is under the p-base. A collector includes an n+ sinker (115) extending from the semiconductor surface to the n+ buried layer (126) including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter (150) has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer (159) on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap (150c), which cuts a metal line and/or the silicide layer of the stack.

Abstract translation: 在所描述的示例中，分段双极晶体管（100）在半导体表面（106）中包括p基极，包括至少一个具有基底金属/硅化物堆叠的p基指（140），所述基底金属/硅化物堆叠包括接触硅化物 （140）的半导体表面上的层（159）。 n +掩埋层（126）位于p基底之下。 收集器包括从半导体表面延伸到n +掩埋层（126）的n +沉降片（115），其包括具有集电极金属/硅化物堆叠的集电极指状物，所述集电极金属/硅化物堆叠包括与集电极的半导体表面上的硅化物层接触的集电极金属线 手指。 n +发射极（150）具有至少一个发射极指，其包括与发射极指状物的半导体表面上的硅化物层（159）接触的发射极金属/硅化物堆叠。 发射极金属/硅化物堆叠和/或集电极金属/硅化物堆叠包括具有间隙（150c）的分割，其切割叠层的金属线和/或硅化物层。

公开(公告)号：WO2015103300A1

公开(公告)日：2015-07-09

申请号：PCT/US2014/072813

申请日：2014-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： REITSMA, George, P.

IPC: G01P3/42 ,  G01R33/00

CPC classification number: G01D5/20 ,  G01D5/2006 ,  G01M13/021 ,  G01P3/488 ,  G01R33/02

Abstract: Described examples include an inductive gear sensing system suitable for sensing gear (gear tooth) movement, such as a combination of speed, direction and position, based on differential sensor response waveforms. Example embodiments of inductive gear sensing with differential sensor response for different gear (10) configurations include generating differential pulsed/phased sensor response signals from dual differential sensors (101, 102) based on axial (proximity-type) sensing, and generating asymmetrical response signals from a single sensor based on lateral and axial sensing with either asymmetrical gear teeth or an asymmetrical sensor or a combination of both.

Abstract translation: 所描述的示例包括适于基于差分传感器响应波形来感测齿轮（齿轮齿）运动的感应齿轮传感系统，例如速度，方向和位置的组合。 针对不同齿轮（10）配置的差分传感器响应的感应齿轮传感的示例实施例包括基于轴向（接近型）感测从双差动传感器（101,102）生成差分脉冲/定相传感器响应信号，并产生非对称响应信号 基于具有不对称齿轮齿或不对称传感器或两者的组合的侧向和轴向感测的单个传感器。

公开(公告)号：WO2015053968A1

公开(公告)日：2015-04-16

申请号：PCT/US2014/057974

申请日：2014-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： TIWARI, Ashutosh ,  DHAM, Ish, Kumar ,  MURTHY, Pranav ,  BANSAL, Virendra, Brijlal

IPC: G06F13/42

CPC classification number: H03K5/159 ,  H03K5/131

Abstract: In described examples, an integrated circuit (IC) (100) includes input/output (I/O) terminals (106) through which signals pass into or out of the IC (100). Also, the IC (100) includes an I/O timing module (102) configured to add propagation delay to signals passing between the I/O terminals (106) and I/O subsystems (104) of the IC (100). The I/O timing module (102) includes delay elements associated with each of the I/O terminals (106), a control register associated with each of the I/O terminals (106), a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal (106). The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals (106) by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract translation: 在所描述的示例中，集成电路（IC）（100）包括信号通过或流出IC（100）的输入/输出（I / O）端子（106）。 此外，IC（100）还包括I / O定时模块（102），其被配置为将传播延迟添加到通过IC（100）的I / O端子（106）和I / O子系统（104）之间的信号。 I / O定时模块（102）包括与每个I / O终端（106）相关联的延迟元件，与每个I / O终端（106）相关联的控制寄存器，存储器和I / O延迟控制 逻辑。 控制寄存器耦合到与I / O端子（106）相关联的每个延迟元件。 存储器用延迟信息编码。 I / O延迟控制逻辑被配置为通过基于存储在所述I / O终端中的延迟信息来选择要应用哪个延迟元件来产生传播延迟来初始化与每个I / O终端（106）相关联的传播延迟 记忆。

公开(公告)号：WO2015021188A1

公开(公告)日：2015-02-12

申请号：PCT/US2014/049991

申请日：2014-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： FARBER, David, Gerald ,  LII, Tom ,  KIRKPATRICK, Brian, K.

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: In described examples, an integrated circuit (100) is formed to include a first MOS transistor (104) having a first polarity and a second MOS transistor (106) having a second, opposite, polarity. A layer of silicon-doped boron nitride (136) is formed over the first MOS transistor (104) and the second MOS transistor (106). The layer of silicon-doped boron nitride (136) is removed from over the first MOS transistor (104). Epitaxial source and drain regions (156) are formed adjacent to spacers (146) of the first MOS transistor (104).

Abstract translation: 在所述的例子中，集成电路（100）被形成为包括具有第一极性的第一MOS晶体管（104）和具有第二相反极性的第二MOS晶体管（106）。 在第一MOS晶体管（104）和第二MOS晶体管（106）之上形成硅掺杂氮化硼层（136）。 掺杂硅的氮化硼层（136）从第一MOS晶体管（104）上方被去除。 形成与第一MOS晶体管（104）的间隔物（146）相邻的外延源极和漏极区（156）。