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    SCANNING OPHTHALMIC FIXATION METHOD AND APPARATUS
    82.
    发明申请
    SCANNING OPHTHALMIC FIXATION METHOD AND APPARATUS 审中-公开
    扫描光学固定方法和装置

    公开(公告)号：WO2005122872A2

    公开(公告)日：2005-12-29

    申请号：PCT/US2005/020419

    申请日：2005-06-09

    Applicant: OPTIMEDICA CORPORATION ,  WILTBERGER, Michael, W. ,  ANDERSEN, Dan, E.

    Inventor： WILTBERGER, Michael, W. ,  ANDERSEN, Dan, E.

    IPC: A61B3/10

    CPC classification number: A61B3/0091 ,  A61B3/102

    Abstract: An apparatus and method for treating and/or diagnosing a patient's eye. A light source produces fixation light and procedure light. A scanning device deflects the fixation light to produce a fixation pattern of the fixation light on the eye, and deflects the procedure light to produce a procedure pattern of the procedure light on the eye. A controller controls the scanning device such that the fixation and procedure patterns move relative to each other, and/or the fixation pattern dynamically changes.

    Abstract translation: 一种用于治疗和/或诊断患者眼睛的装置和方法。 光源产生固定光和程序灯。 扫描装置偏转固定光以产生眼睛上的固定光的固定图案，并偏转程序光，以产生眼睛上过程光的过程模式。 控制器控制扫描装置，使得固定和过程模式相对于彼此移动，和/或固定模式动态地改变。

    TWO TRANSISTOR FINFET-BASED SPLIT GATE NON-VOLATILE FLOATING GATE FLASH MEMORY AND METHOD OF FABRICATION
    83.
    发明申请
    TWO TRANSISTOR FINFET-BASED SPLIT GATE NON-VOLATILE FLOATING GATE FLASH MEMORY AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：WO2019182681A2

    公开(公告)日：2019-09-26

    申请号：PCT/US2019/014816

    申请日：2019-01-23

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： JOURBA, Serguei ,  DECOBERT, Catherine ,  FENG, Zhou ,  KIM, Jimho ,  LIU, Xian ,  DO, Nhan

    IPC: H01L27/11524

    Abstract: A non- volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

    TWIN BIT NON-VOLATILE MEMORY CELLS WITH FLOATING GATES IN SUBSTRATE TRENCHES
    84.
    发明申请
    TWIN BIT NON-VOLATILE MEMORY CELLS WITH FLOATING GATES IN SUBSTRATE TRENCHES 审中-公开

    公开(公告)号：WO2019135813A1

    公开(公告)日：2019-07-11

    申请号：PCT/US2018/056833

    申请日：2018-10-22

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： WANG, Chunming ,  LIU, Andy ,  LIU, Xian ,  XING, Leo ,  DAO, Melvin ,  DO, Nhan

    IPC: H01L21/02 ,  H01L29/02 ,  H01L27/04

    Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

    METHOD OF INTEGRATING FINFET CMOS DEVICES WITH EMBEDDED NONVOLATILE MEMORY CELLS
    87.
    发明申请
    METHOD OF INTEGRATING FINFET CMOS DEVICES WITH EMBEDDED NONVOLATILE MEMORY CELLS 审中-公开
    集成FINFET CMOS器件与嵌入式非易失性存储器单元的方法

    公开(公告)号：WO2017204937A1

    公开(公告)日：2017-11-30

    申请号：PCT/US2017/028034

    申请日：2017-04-18

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TRAN, Hieu, Van ,  DO, Nhan

    IPC: H01L29/66 ,  H01L29/792 ,  H01L29/788

    Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.

    Abstract translation: 一种在平面衬底表面上方形成具有存储器单元的存储器件以及在鳍状衬底表面部分上方形成FinFET逻辑器件的方法，所述方法包括在先前形成的浮置栅极，擦除栅极，字线 然后在衬底的存储器单元部分中形成多晶硅层和多晶硅层和源极区，然后在衬底的表面形成鳍，并在衬底的逻辑部分中沿着鳍形成逻辑门，然后除去保护层，并完成字线门的形成 在衬底的存储器单元部分中的字线多晶硅和漏极区。

    FLASH MEMORY ARRAY WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE
    88.
    发明申请
    FLASH MEMORY ARRAY WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE 审中-公开
    具有单独存储单元的闪存阵列读取，编程和擦除

    公开(公告)号：WO2017200710A1

    公开(公告)日：2017-11-23

    申请号：PCT/US2017/029024

    申请日：2017-04-23

    Applicant: SILICON STORAGE TECHNOLOGY, INC. ,  THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： GUO, Xinjie ,  BAYAT, Farnood, Merrikh ,  STRUKOV, Dmitri ,  DO, Nhan ,  TRAN, Hieu, Van ,  TIWARI, Vipin

    IPC: G11C7/00 ,  G11C16/04 ,  G11C16/24

    Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

    Abstract translation:

    提供单独存储单元读取，写入和擦除的存储器件。 在以行和列排列的存储器单元阵列中，存储器单元的每列包括列位线，偶数行单元的第一列控制栅极线和奇数行单元的第二列控制栅极线。 每行存储器单元包括一行源极线。 在另一个实施例中，每列存储器单元包括列位线和列源极线。 每行存储器单元包括行控制栅极线。 在又一个实施例中，每列存储器单元包括列位线和列擦除栅极线。 每行存储器单元包括行源极线，行控制栅极线和行选择栅极线。

    METHOD OF FORMING PAIRS OF THREE-GATE NON-VOLATILE FLASH MEMORY CELLS USING TWO POLYSILICON DEPOSITION STEPS
    89.
    发明申请
    METHOD OF FORMING PAIRS OF THREE-GATE NON-VOLATILE FLASH MEMORY CELLS USING TWO POLYSILICON DEPOSITION STEPS 审中-公开
    使用两个多晶硅沉积步骤形成一对三栅非易失性闪存细胞的方法

    公开(公告)号：WO2017184315A1

    公开(公告)日：2017-10-26

    申请号：PCT/US2017/025263

    申请日：2017-03-31

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： ZHOU, Feng ,  LIU, Xian ,  SU, Chien-Sheng ,  DO, Nhan ,  WANG, Chunming

    IPC: H01L29/788 ,  H01L29/66

    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

    Abstract translation: 使用两个多晶硅沉积来形成非易失性存储器单元对的简化方法。 在第一多晶硅沉积工艺中，第一多晶硅层形成在半导体衬底上并与半导体衬底绝缘。 在第一多晶硅层上形成一对间隔开的绝缘块。 第一多晶硅层的暴露部分被去除，同时保持第一多晶硅层的一对多晶硅块分别设置在一对绝缘块中的一个下面。 在第二多晶硅沉积工艺中在衬底和该对绝缘块上形成第二多晶硅层。 在保持第一多晶硅块（设置在所述一对绝缘块之间），第二多晶硅块（设置为与一个绝缘块的外侧相邻）和第三多晶硅块（设置为与第二多晶硅块的外侧相邻）的同时，去除第二多晶硅层的部分 另一个绝缘块的一面）。

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