公开(公告)号：WO2019217022A1

公开(公告)日：2019-11-14

申请号：PCT/US2019/026671

申请日：2019-04-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： DO, Nhan ,  SU, Chien-Sheng ,  YANG, Jeng-Wei

IPC: H01L29/66 ,  H01L29/788

Abstract: A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.

公开(公告)号：WO2014031286A2

公开(公告)日：2014-02-27

申请号：PCT/US2013/052457

申请日：2013-07-29

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： LIU, Xian ,  TADAYONI, Mandana ,  SU, Chien-Sheng ,  DO, Nhan

IPC: H01L21/04

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

Abstract translation: 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。

公开(公告)号：WO2016148873A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/019860

申请日：2016-02-26

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  TRAN, Hieu Van ,  DO, Nhan ,  CHEN, Chun-Ming

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿着两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：WO2015112282A1

公开(公告)日：2015-07-30

申请号：PCT/US2014/070674

申请日：2014-12-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

公开(公告)号：WO2017070018A1

公开(公告)日：2017-04-27

申请号：PCT/US2016/057101

申请日：2016-10-14

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/02 ,  G11C11/34 ,  G06F13/00

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Abstract translation: 形成非易失性存储器单元的方法包括在衬底中形成间隔开的第一区域和第二区域，在其间限定沟道区域。 浮置栅极形成在沟道区域的第一部分之上以及第一区域的一部分之上，其中浮置栅极包括布置在第一区域之上的尖锐边缘。 隧道氧化层围绕尖锐边缘形成。 擦除栅极形成在第一区域上方，其中擦除栅极包括面向尖锐边缘的凹口，并且其中凹口通过隧道氧化物层与尖锐边缘绝缘。 字线门形成在与第二区域相邻的沟道区域的第二部分之上。 字线门的形成是在形成隧道氧化层和擦除门之后进行的。

公开(公告)号：WO2016118785A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/014393

申请日：2016-01-21

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  CHEN, Chun-Ming ,  WU, Man-Tang ,  ZHOU, Feng ,  LIU, Xian ,  SU, Chien-Sheng ,  DO, Nhan

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。

公开(公告)号：WO2013022618A1

公开(公告)日：2013-02-14

申请号：PCT/US2012/048603

申请日：2012-07-27

Applicant: SILICON STORAGE TECHNOLOGY, INC. ,  KOTOV, Alexander ,  SU, Chien-Sheng

Inventor： KOTOV, Alexander ,  SU, Chien-Sheng

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

Abstract: A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

Abstract translation: 一种非易失性存储器，包括第一导电类型的衬底，其中形成有第二和第二间隔开的区域，第二导电类型在其间具有沟道区域。 多晶硅金属栅极字线被定位在沟道区的第一部分上方并且通过高K电介质层与其隔开。 字线的金属部分紧邻高K电介质层。 多晶硅浮栅直接与字线相邻并且与字线间隔开，并位于沟道区的另一部分之上并与之绝缘。 多晶硅耦合栅极位于浮栅上并与浮栅隔绝。 多晶硅擦除栅极位于浮动栅极的另一侧并且与浮栅绝缘，位于第二区域的上方并与第二区域绝缘，并且紧邻耦合栅极的另一侧，但与其隔开。

公开(公告)号：WO2019112756A1

公开(公告)日：2019-06-13

申请号：PCT/US2018/060181

申请日：2018-11-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/04 ,  H01L27/115

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：WO2018031089A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/033243

申请日：2017-05-18

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TRAN, Hieu Van ,  DO, Nhan

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/41 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

Abstract translation: 一种形成存储器件的方法，该方法包括：在半导体衬底上形成第一绝缘层;在第一绝缘层上形成导电材料层;在导电材料层上形成绝缘块;形成 沿绝缘块的侧表面和导电材料层上的绝缘间隔体，蚀刻导电材料层以形成直接设置在绝缘块和绝缘间隔体下方的导电材料块，去除绝缘间隔体，形成第二绝缘体 其具有第一部分和第二部分，第一部分缠绕在导电材料块的暴露的上边缘上，第二部分设置在第一绝缘层的第一部分上，并形成与导电材料块绝缘的导电块， 第二绝缘层并且通过第一和第二绝缘层从基板上。

公开(公告)号：WO2016141060A1

公开(公告)日：2016-09-09

申请号：PCT/US2016/020455

申请日：2016-03-02

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chung-Ming ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  WU, Man-Tang ,  DO, Nhan

IPC: H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices are formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract translation: 存储器件包括具有存储器（16）和逻辑器件区域（18）的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 多个逻辑器件形成在逻辑器件区域中，每个逻辑器件包括其间具有第二沟道区的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。