公开(公告)号：WO2016148873A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/019860

申请日：2016-02-26

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  TRAN, Hieu Van ,  DO, Nhan ,  CHEN, Chun-Ming

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿着两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：WO2017070018A1

公开(公告)日：2017-04-27

申请号：PCT/US2016/057101

申请日：2016-10-14

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/02 ,  G11C11/34 ,  G06F13/00

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Abstract translation: 形成非易失性存储器单元的方法包括在衬底中形成间隔开的第一区域和第二区域，在其间限定沟道区域。 浮置栅极形成在沟道区域的第一部分之上以及第一区域的一部分之上，其中浮置栅极包括布置在第一区域之上的尖锐边缘。 隧道氧化层围绕尖锐边缘形成。 擦除栅极形成在第一区域上方，其中擦除栅极包括面向尖锐边缘的凹口，并且其中凹口通过隧道氧化物层与尖锐边缘绝缘。 字线门形成在与第二区域相邻的沟道区域的第二部分之上。 字线门的形成是在形成隧道氧化层和擦除门之后进行的。

公开(公告)号：WO2016118785A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/014393

申请日：2016-01-21

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  CHEN, Chun-Ming ,  WU, Man-Tang ,  ZHOU, Feng ,  LIU, Xian ,  SU, Chien-Sheng ,  DO, Nhan

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。

公开(公告)号：WO2019070428A1

公开(公告)日：2019-04-11

申请号：PCT/US2018/052302

申请日：2018-09-21

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  CHEN, Chun-Ming ,  WU, Man-Tang ,  FAN, Chen-Chih ,  DO, Nhan

IPC: G11C16/10 ,  G11C16/16 ,  H01L27/115 ,  H01L29/423

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

公开(公告)号：WO2017204937A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/028034

申请日：2017-04-18

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TRAN, Hieu, Van ,  DO, Nhan

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/788

Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.

Abstract translation: 一种在平面衬底表面上方形成具有存储器单元的存储器件以及在鳍状衬底表面部分上方形成FinFET逻辑器件的方法，所述方法包括在先前形成的浮置栅极，擦除栅极，字线 然后在衬底的存储器单元部分中形成多晶硅层和多晶硅层和源极区，然后在衬底的表面形成鳍，并在衬底的逻辑部分中沿着鳍形成逻辑门，然后除去保护层，并完成字线门的形成 在衬底的存储器单元部分中的字线多晶硅和漏极区。

公开(公告)号：WO2016111742A1

公开(公告)日：2016-07-14

申请号：PCT/US2015/059443

申请日：2015-11-06

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04

CPC classification number: H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/7885

Abstract: A non- volatile memory cell including a substrate having first and second regions with a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over and insulated from a second portion of the channel region which is adjacent to the second region. The select gate includes a block of polysilicon material and a work function metal material layer extending along bottom and side surfaces of the polysilicon material block. The select gate is insulated from the second portion of the channel region by a silicon dioxide layer and a high K insulating material layer. A control gate is disposed over and insulated from the floating gate, and an erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

Abstract translation: 一种非易失性存储单元，包括具有其间具有沟道区域的第一和第二区域的衬底。 浮置栅极设置在与第一区域相邻的沟道区域的第一部分之上并与其绝缘。 选择栅极设置在与第二区域相邻的沟道区域的第二部分之上并与其绝缘。 选择栅极包括多晶硅材料块和沿着多晶硅材料块的底部和侧表面延伸的功函数金属材料层。 选择栅极通过二氧化硅层和高K绝缘材料层与沟道区的第二部分绝缘。 控制栅极设置在浮动栅极上并与浮动栅极绝缘，并且擦除栅极设置在第一区域的上方并与第一区域绝缘，并且横向地设置在与浮动栅极相邻并与其隔离的位置。

公开(公告)号：WO2019221867A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/027760

申请日：2019-04-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： LIANG, Hsuan ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  DO, Nhan ,  TRAN, Hieu, Van

IPC: G11C16/16 ,  G11C16/04

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

公开(公告)号：WO2019112756A1

公开(公告)日：2019-06-13

申请号：PCT/US2018/060181

申请日：2018-11-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  SU, Chien-Sheng ,  DO, Nhan

IPC: G11C16/04 ,  H01L27/115

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：WO2018031089A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/033243

申请日：2017-05-18

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TRAN, Hieu Van ,  DO, Nhan

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/41 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

Abstract translation: 一种形成存储器件的方法，该方法包括：在半导体衬底上形成第一绝缘层;在第一绝缘层上形成导电材料层;在导电材料层上形成绝缘块;形成 沿绝缘块的侧表面和导电材料层上的绝缘间隔体，蚀刻导电材料层以形成直接设置在绝缘块和绝缘间隔体下方的导电材料块，去除绝缘间隔体，形成第二绝缘体 其具有第一部分和第二部分，第一部分缠绕在导电材料块的暴露的上边缘上，第二部分设置在第一绝缘层的第一部分上，并形成与导电材料块绝缘的导电块， 第二绝缘层并且通过第一和第二绝缘层从基板上。

公开(公告)号：WO2016141060A1

公开(公告)日：2016-09-09

申请号：PCT/US2016/020455

申请日：2016-03-02

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chung-Ming ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  WU, Man-Tang ,  DO, Nhan

IPC: H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices are formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract translation: 存储器件包括具有存储器（16）和逻辑器件区域（18）的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 多个逻辑器件形成在逻辑器件区域中，每个逻辑器件包括其间具有第二沟道区的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。