摘要:
Techniques are described for performing constrained three-dimensional (3D) color prediction for color gamut scalability in video coding. Color prediction techniques for color gamut scalability may be used by video coders to generate inter-layer reference pictures when a color gamut for a reference layer of video data is different than a color gamut for an enhancement layer of the video data, or when a bit depth of the reference layer is different than a bit depth of the enhancement layer. According to the techniques, a video coder may perform 3D color prediction with constrained bit depths of input and output color components of the 3D lookup table. According to further techniques, in the case of multiple layers, a video coder may perform 3D color prediction with constrained application to reference pictures in only one or more identified reference layers.
摘要:
Techniques are described for signaling information used to generate three-dimensional (3D) color lookup tables for color gamut scalability in multi-layer video coding. A lower layer of video data may include color data in a first color gamut and a higher layer of the video data may include color data in a second color gamut. To generate inter-layer reference pictures, a video encoder or video decoder performs color prediction using a 3D lookup table to convert the color data of a reference picture in the first color gamut to the second color gamut. According to the techniques, a video encoder may encode partition information and/or color values of a 3D lookup table generated for color gamut scalability. A video decoder may decode the partition information and/or color values to generate the 3D lookup table in order to perform color gamut scalability.
摘要:
The present invention provides a system (and corresponding method and devices) for encoding an ungrouped signal into a plurality of grouped signals, wherein the ungrouped signal comprises at least a video service. The system further comprises: - a first encoding means provided in a production system configured to execute a first encoding of the ungrouped video signal into a first encoded grouped signal (140) and to associate encoding information (140) with the first encoded signal; - a second encoding means (160) provided in a distribution system, wherein the second encoding means is separate from said first encoding means and is configured to execute a plurality of second encodings so as to correspondingly obtain the plurality of grouped signals (180), each of the plurality of grouped signals (180) characterised by a corresponding predetermined property, wherein the second encodings are performed on the basis of said first encoded signal using the encoding information; - a connection means configured to transmit the encoding information (140) from the first encoding means (150) to the second encoding means (160), wherein the encoding information (140) comprises information on the first encoding.
摘要:
An encoding apparatus employing both a CPU and a chip or circuit dedicated to the encoding is disclosed. The encoding apparatus includes a hardware encoder 151 and a software encoder 152. The hardware encoder 151 is configured by hardware dedicated to the encoding and encodes a portion of AV data. The software encoder 152 encodes another portion of the AV data in parallel to the encoding process of the hardware encoder 151 by the use of a CPU 10. A position detector 18 detects a switching position of an allocation destination in the AV data. A data allocator 14 allocates sections of the AV data divided by the switching position to both encoders 151 and 152. A synthesizer 16 arranges the encoded AV data in a predetermined sequence to synthesize a series of encoded AV data. An output unit 17 outputs the series of encoded AV data.
摘要:
Variable length decoding of DCT coefficients in MPEG video data is performed using a standard processor (400) and a small look-up table (LUT 530). The processor performs (520) an integer to floating point conversion on a portion the received bitstream (BS). By this step, lengthy codewords with many leading zeros, which are common in the codebook, are represented in a compressed form by the exponent and mantissa fields (EXP, MAN) of the floating point result (FP). The relevant bits are extracted and used as an index (IX) to address the LUT. This avoids cumbersome bit-oriented logic, while also avoiding a very large LUT that would otherwise be required to represent the same codebook. The entire LUT may thus reside in cache memory (410). In a VLIW processor implementation, decoding of one token is pipelined with the inverse scan and inverse quantisation step of the preceding token(s).
摘要:
A circuit in which encoding is performed at high rate with low power consumption according to DVI (Digital Visual Interface) standards using a small quantity of hardware. In the DVI encoding circuit, a number-of-levels comparison circuit (22) for comparing the number of "H" level bits of an input signal of the encoding circuit with that of "L" level bits has an input of 7 bits. Four bits of the output of a number-of-transition reducing circuit (23) for reducing the number of transitions between adjacent bits can be inverted based on the output from the number-of-levels comparison circuit (22). A DC balance circuit (24) for balancing the output signal in a DC manner comprises a 4-bit register (31), a number-of-levels difference calculating circuit (27), a condition deciding circuit (28), a bit inverting circuit (29), and an adder circuit (30). The number-of-levels difference calculating circuit (27) receives an 8-bit output from the circuit (23) and a 4-bit input signal to the encoding circuit.
摘要:
A demodulator of digital terrestrial broadcast or the like for transmitting coded digital video and audio information in packet form comprises a synchronous code pattern detecting circuit for detecting the segment synchronous code pattern from the most significant bit signal of the reception packet data, a symbol number counter circuit for counting the number of symbol data in the reception packet data, a synchronism detection establishing circuit for judging the true segment synchronous code pattern by obtaining the segment synchronous code pattern from the synchronous code pattern detecting circuit when the symbol number counter circuit finishes counting of a specified number, and a synchronism detection protection counter circuit for detecting and establishing the segment synchronous signal in the reception data from the output of the synchronous code pattern detecting circuit and count-up of specified number of the symbol number counter circuit. In this constitution, even in an inferior environment for receiving broadcast such as deterioration of C/N of signal due to weak electric field, or strong ghost or multipath characteristic of terrestrial waves, the digital broadcast demodulator capable of processing packet synchronism detection, AGC, and clock regeneration stably and precisely is presented.