公开(公告)号：WO2021119252A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/064204

申请日：2020-12-10

Applicant: SUNPOWER CORPORATION

Inventor： KIM, Taeseok ,  SMITH, David

IPC: H01L31/02 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/18

Abstract: Aligned metallization approaches for fabricating solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a semiconductor layer over a semiconductor substrate. A first plurality of discrete openings is in the semiconductor layer and exposes corresponding discrete portions of the semiconductor substrate. A plurality of doped regions is in the semiconductor substrate and corresponds to the first plurality of discrete openings. An insulating layer is over the semiconductor layer and is in the first plurality of discrete openings. A second plurality of discrete openings is in the insulating layer and exposes corresponding portions of the plurality of doped regions. Each one of the second plurality of discrete openings is entirely within a perimeter of a corresponding one of the first plurality of discrete openings. A plurality of conductive contacts is in the second plurality of discrete openings and is on the plurality of doped regions.

公开(公告)号：WO2019190463A1

公开(公告)日：2019-10-03

申请号：PCT/US2018/024364

申请日：2018-03-26

Applicant: INTEL CORPORATION ,  HAN, Eungnak ,  MAHDI, Tayseer ,  HOURANI, Rami ,  SINGH, Gurpreet ,  GSTREIN, Florian

Inventor： HAN, Eungnak ,  MAHDI, Tayseer ,  HOURANI, Rami ,  SINGH, Gurpreet ,  GSTREIN, Florian

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  G03F7/20

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

公开(公告)号：WO2019182596A1

公开(公告)日：2019-09-26

申请号：PCT/US2018/023753

申请日：2018-03-22

Applicant: INTEL CORPORATION ,  WEBER, Cory E. ,  KENNEL, Harold W. ,  RACHMADY, Willy ,  DEWEY, Gilbert

Inventor： WEBER, Cory E. ,  KENNEL, Harold W. ,  RACHMADY, Willy ,  DEWEY, Gilbert

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：WO2019054993A1

公开(公告)日：2019-03-21

申请号：PCT/US2017/051215

申请日：2017-09-12

Applicant: INTEL CORPORATION ,  MAJHI, Prashant ,  DOYLE, Brian S. ,  KARPOV, Elijah V. ,  SHARMA, Abhishek A. ,  PILLARISETTY, Ravi

Inventor： MAJHI, Prashant ,  DOYLE, Brian S. ,  KARPOV, Elijah V. ,  SHARMA, Abhishek A. ,  PILLARISETTY, Ravi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06

Abstract: Ferroelectric field effect transistors (FeFETs) having ambipolar channels are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of an ambipolar material. A ferroelectric oxide material is above the channel layer. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

公开(公告)号：WO2019009874A1

公开(公告)日：2019-01-10

申请号：PCT/US2017/040553

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： DOGIAMIS, Georgios ,  OSTER, Sasha ,  KAMGAING, Telesphor ,  EWY, Erich ,  SHOEMAKER, Kenneth ,  ELSHERBINI, Adel ,  SWAN, Johanna

IPC: H05K5/00 ,  H01L23/58 ,  B60R16/02

Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

公开(公告)号：WO2019009873A1

公开(公告)日：2019-01-10

申请号：PCT/US2017/040552

申请日：2017-07-01

Applicant: INTEL CORPORATION ,  LIN, Kevin ,  LE, Van ,  KAVALIEROS, Jack

Inventor： LIN, Kevin ,  LE, Van ,  KAVALIEROS, Jack

IPC: H01L29/786 ,  H01L21/768

Abstract: Embodiments of the invention include thin-film transistors and methods of making such devices with damascene processes. In an embodiment the thin-film transistor (TFT) device includes an interlayer dielectric (ILD) layer, where a trench is formed into the ILD layer. In an embodiment a TFT semiconductor layer formed in the trench, wherein extensions of the TFT semiconductor layer extend up sidewalls of the trench. In an embodiment, a capping layer formed over a top surface of the TFT semiconductor layer. Additional embodiments may include a source electrode and a drain electrode, where the source electrode and the drain electrode contact a surface of the TFT semiconductor layer, and a gate electrode separated from a surface of the TFT semiconductor layer by a gate dielectric layer.

公开(公告)号：WO2019005163A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040504

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  PILLARISETTY, Ravi ,  SHARMA, Abhishek A. ,  DEWEY, Gilbert ,  LE, Van H. ,  KAVALIEROS, Jack T.

Inventor： PILLARISETTY, Ravi ,  SHARMA, Abhishek A. ,  DEWEY, Gilbert ,  LE, Van H. ,  KAVALIEROS, Jack T.

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/1233

Abstract: A memory structure includes a conductive interconnect disposed above a substrate, a memory device disposed above the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. For memory device and fabrication enablement, a top hat electrode is disposed on the memory device. The top hat electrode has sidewalls, a lowermost surface and an uppermost surface. The sidewalls of the top hat electrode extend beyond the sidewalls of the memory device. The top hat electrode has a lowermost surface area that is larger than an area of the uppermost surface of the memory device. A second conductive interconnect is disposed on the top hat electrode. The second conductive interconnect includes a via having sidewalls and a lowermost surface that is in contact with the uppermost surface of the top hat electrode.

公开(公告)号：WO2019005159A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040498

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  DOYLE, Brian S. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  SHARMA, Abhishek A. ,  MAJHI, Prashant ,  KARPOV, Elijah V.

Inventor： DOYLE, Brian S. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  SHARMA, Abhishek A. ,  MAJHI, Prashant ,  KARPOV, Elijah V.

IPC: H01L27/02 ,  H01L21/66

CPC classification number: H01L27/0288

Abstract: Electric static device (ESD) protection is disclosed including insulator-metal transition material for ESD protection. In one example, an apparatus includes a device under test (DUT) coupled to a rail and ground, and an insulator-metal transition (IMT) device coupled to the DUT to protect the DUT from electrostatic discharge (ESD). The IMT device is configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the IMT device. The threshold voltage of the IMT device is greater than a power supply voltage to the DUT. The IMT device is configured to turn on when the threshold voltage of the IMT device is exceeded caused by a positive or negative ESD pulse and sinks a current to ground or a voltage source. The IMT device includes a top electrode layer, a bottom electrode layer, and an insulator-metal transition material layer formed in between the top and bottom electrode layers. The top electrode layer of the IMT device is coupled to an input of the DUT and the bottom electrode layer is coupled to the ground for the DUT.

公开(公告)号：WO2019005107A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040286

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： CHANG, Je-Young ,  JHA, Chandra M. ,  DEVASENATHIPATHY, Shankar ,  EID, Feras ,  JOHNSON, John C.

IPC: H01L23/367

Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

公开(公告)号：WO2019005019A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/039573

申请日：2017-06-27

Applicant: INTEL CORPORATION ,  KARPOV, Elijah V. ,  MAJHI, Prashant ,  DOYLE, Brian S.

Inventor： KARPOV, Elijah V. ,  MAJHI, Prashant ,  DOYLE, Brian S.

IPC: G11C11/22 ,  H01L27/11502

CPC classification number: G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2259 ,  H01L27/11507

Abstract: Cross-point ferroelectric memory arrays, and methods of fabricating cross-point ferroelectric memory arrays, are described. In an example, an integrated circuit structure includes a first plurality of conductive lines along a first direction above a substrate. A plurality of memory elements is on individual ones of the first plurality of conductive lines, individual ones of the plurality of memory elements including a bottom electrode, a ferroelectric oxide material on the bottom electrode, and a top electrode on the ferroelectric oxide material. A second plurality of conductive lines is on the plurality of memory elements, the second plurality of conductive lines along a second direction orthogonal to the first direction.