公开(公告)号：WO2018118089A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068582

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  HAN, Eungnak ,  HOURANI, Rami ,  GSTREIN, Florian ,  SINGH, Gurpreet ,  CLENDENNING, Scott B. ,  LIN, Kevin L. ,  CHANDHOK, Manish

Inventor： HAN, Eungnak ,  HOURANI, Rami ,  GSTREIN, Florian ,  SINGH, Gurpreet ,  CLENDENNING, Scott B. ,  LIN, Kevin L. ,  CHANDHOK, Manish

IPC: H01L21/768 ,  H01L21/033

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：WO2014209327A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048307

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  HOURANI, Rami ,  HAN, Eungnak ,  BLACKWELL, James M.

Inventor： BRISTOL, Robert L. ,  HOURANI, Rami ,  HAN, Eungnak ,  BLACKWELL, James M.

IPC: H01L21/027 ,  H01L21/28

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基板的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：WO2019190463A1

公开(公告)日：2019-10-03

申请号：PCT/US2018/024364

申请日：2018-03-26

Applicant: INTEL CORPORATION ,  HAN, Eungnak ,  MAHDI, Tayseer ,  HOURANI, Rami ,  SINGH, Gurpreet ,  GSTREIN, Florian

Inventor： HAN, Eungnak ,  MAHDI, Tayseer ,  HOURANI, Rami ,  SINGH, Gurpreet ,  GSTREIN, Florian

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  G03F7/20

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

公开(公告)号：WO2015047345A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062456

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

IPC: H01L21/31

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。